/** Number of general purpose registers (VS, WM, etc) */
#define BRW_MAX_GRF 128
+/**
+ * First GRF used for the MRF hack.
+ *
+ * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
+ * haven't converted our compiler to be aware of this, so it asks for MRFs and
+ * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
+ * register allocators have to be careful of this to avoid corrupting the "MRF"s
+ * with actual GRF allocations.
+ */
+#define GEN7_MRF_HACK_START 112.
+
/** Number of message register file registers */
#define BRW_MAX_MRF 16
GLuint x_offset:7;
} ss5;
- struct {
- GLuint pad; /* Multisample Control Surface stuff */
+ union {
+ GLuint raw_data;
+ struct {
+ GLuint y_offset_for_uv_plane:14;
+ GLuint pad1:2;
+ GLuint x_offset_for_uv_plane:14;
+ GLuint pad0:2;
+ } planar; /** Interpretation when Surface Format == PLANAR */
+ struct {
+ GLuint mcs_enable:1;
+ GLuint append_counter_enable:1;
+ GLuint pad:4;
+ GLuint append_counter_address:26;
+ } mcs_disabled; /** Interpretation when mcs_enable == 0 */
+ struct {
+ GLuint mcs_enable:1;
+ GLuint pad:2;
+ GLuint mcs_surface_pitch:9;
+ GLuint mcs_base_address:20;
+ } mcs_enabled; /** Interpretation when mcs_enable == 1 */
} ss6;
struct {
GLuint resource_min_lod:12;
- GLuint pad0:16;
+
+ /* Only on Haswell */
+ GLuint pad0:4;
+ GLuint shader_channel_select_a:3;
+ GLuint shader_channel_select_b:3;
+ GLuint shader_channel_select_g:3;
+ GLuint shader_channel_select_r:3;
+
GLuint alpha_clear_color:1;
GLuint blue_clear_color:1;
GLuint green_clear_color:1;
} ve1;
};
-#define BRW_VEP_MAX 18
-
struct brw_urb_immediate {
GLuint opcode:4;
GLuint offset:6;
GLint jump_count:16;
} branch_gen6;
+
+ struct {
+ GLuint dest_reg_file:1;
+ GLuint flag_subreg_num:1;
+ GLuint pad0:2;
+ GLuint src0_abs:1;
+ GLuint src0_negate:1;
+ GLuint src1_abs:1;
+ GLuint src1_negate:1;
+ GLuint src2_abs:1;
+ GLuint src2_negate:1;
+ GLuint pad1:7;
+ GLuint dest_writemask:4;
+ GLuint dest_subreg_nr:3;
+ GLuint dest_reg_nr:8;
+ } da3src;
+
+ uint32_t ud;
} bits1;
GLuint src0_horiz_stride:2;
GLuint src0_width:3;
GLuint src0_vert_stride:4;
+ GLuint flag_subreg_nr:1;
GLuint flag_reg_nr:1;
- GLuint pad:6;
+ GLuint pad:5;
} da1;
struct
GLuint src0_horiz_stride:2;
GLuint src0_width:3;
GLuint src0_vert_stride:4;
+ GLuint flag_subreg_nr:1;
GLuint flag_reg_nr:1;
- GLuint pad:6;
+ GLuint pad:5;
} ia1;
struct
GLuint src0_swz_w:2;
GLuint pad0:1;
GLuint src0_vert_stride:4;
+ GLuint flag_subreg_nr:1;
GLuint flag_reg_nr:1;
- GLuint pad1:6;
+ GLuint pad1:5;
} da16;
struct
GLuint src0_swz_w:2;
GLuint pad0:1;
GLuint src0_vert_stride:4;
+ GLuint flag_subreg_nr:1;
GLuint flag_reg_nr:1;
- GLuint pad1:6;
+ GLuint pad1:5;
} ia16;
/* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
GLuint sfid:4;
} send_gen5; /* for Ironlake only */
+ struct {
+ GLuint src0_rep_ctrl:1;
+ GLuint src0_swizzle:8;
+ GLuint src0_subreg_nr:3;
+ GLuint src0_reg_nr:8;
+ GLuint pad0:1;
+ GLuint src1_rep_ctrl:1;
+ GLuint src1_swizzle:8;
+ GLuint src1_subreg_nr_low:2;
+ } da3src;
+
+ uint32_t ud;
} bits2;
union
GLuint src1_horiz_stride:2;
GLuint src1_width:3;
GLuint src1_vert_stride:4;
- GLuint flag_reg_nr:1;
- GLuint pad1:6;
+ GLuint pad1:7;
} ia1;
struct
GLuint src1_swz_w:2;
GLuint pad1:1;
GLuint src1_vert_stride:4;
- GLuint flag_reg_nr:1;
- GLuint pad2:6;
+ GLuint pad2:7;
} ia16;
int uip:16;
} break_cont;
+ /**
+ * \defgroup SEND instructions / Message Descriptors
+ *
+ * @{
+ */
+
+ /**
+ * Generic Message Descriptor for Gen4 SEND instructions. The structs
+ * below expand function_control to something specific for their
+ * message. Due to struct packing issues, they duplicate these bits.
+ *
+ * See the G45 PRM, Volume 4, Table 14-15.
+ */
+ struct {
+ GLuint function_control:16;
+ GLuint response_length:4;
+ GLuint msg_length:4;
+ GLuint msg_target:4;
+ GLuint pad1:3;
+ GLuint end_of_thread:1;
+ } generic;
+
+ /**
+ * Generic Message Descriptor for Gen5-7 SEND instructions.
+ *
+ * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
+ * of the information on the SEND instruction is missing from the public
+ * Ironlake PRM.)
+ *
+ * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
+ * According to the SEND instruction description:
+ * "The MSb of the message description, the EOT field, always comes from
+ * bit 127 of the instruction word"...which is bit 31 of this field.
+ */
+ struct {
+ GLuint function_control:19;
+ GLuint header_present:1;
+ GLuint response_length:5;
+ GLuint msg_length:4;
+ GLuint pad1:2;
+ GLuint end_of_thread:1;
+ } generic_gen5;
+
+ /** G45 PRM, Volume 4, Section 6.1.1.1 */
struct {
GLuint function:4;
GLuint int_type:1;
GLuint end_of_thread:1;
} math;
+ /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
struct {
GLuint function:4;
GLuint int_type:1;
GLuint end_of_thread:1;
} math_gen5;
+ /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
struct {
GLuint binding_table_index:8;
GLuint sampler:4;
GLuint end_of_thread:1;
} sampler;
+ /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
struct {
GLuint binding_table_index:8;
GLuint sampler:4;
GLuint end_of_thread:1;
} sampler_g4x;
+ /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
struct {
GLuint binding_table_index:8;
GLuint sampler:4;
GLuint end_of_thread:1;
} urb_gen7;
+ /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
struct {
GLuint binding_table_index:8;
GLuint msg_control:4;
GLuint end_of_thread:1;
} dp_read;
+ /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint end_of_thread:1;
} dp_read_g4x;
+ /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint end_of_thread:1;
} dp_read_gen5;
+ /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint end_of_thread:1;
} dp_write;
+ /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint end_of_thread:1;
} dp_write_gen5;
- /* Sandybridge DP for sample cache, constant cache, render cache */
+ /**
+ * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
+ *
+ * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
+ **/
struct {
GLuint binding_table_index:8;
GLuint msg_control:5;
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
- } dp_sampler_const_cache;
+ } gen6_dp_sampler_const_cache;
+ /**
+ * Message for the Sandybridge Render Cache Data Port.
+ *
+ * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
+ * Section 3.9.2.1.1: Message Descriptor.
+ *
+ * "Slot Group Select" and "Last Render Target" are part of the
+ * 5-bit message control for Render Target Write messages. See
+ * Section 3.9.9.2.1 of the same volume.
+ */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint end_of_thread:1;
} gen6_dp;
- /* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
+ /**
+ * Message for any of the Gen7 Data Port caches.
+ *
+ * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
+ * Data Port Messages / Message Descriptor. Once again, "Slot Group
+ * Select" and "Last Render Target" are part of the 6-bit message
+ * control for Render Target Writes.
+ */
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint slot_group_select:1;
GLuint last_render_target:1;
- GLuint pad0:1;
+ GLuint msg_control_pad:1;
GLuint msg_type:4;
GLuint pad1:1;
GLuint header_present:1;
GLuint pad2:2;
GLuint end_of_thread:1;
} gen7_dp;
+ /** @} */
- /**
- * Message Descriptor for Gen4 SEND instructions (no particular message).
- *
- * See the G45 PRM, Volume 4, Table 14-15.
- */
- struct {
- GLuint function_control:16;
- GLuint response_length:4;
- GLuint msg_length:4;
- GLuint msg_target:4;
- GLuint pad1:3;
- GLuint end_of_thread:1;
- } generic;
-
- /**
- * Message Descriptor for Gen5-7 SEND instructions.
- *
- * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
- * of the information on the SEND instruction is missing from the public
- * Ironlake PRM.)
- *
- * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
- * According to the SEND instruction description:
- * "The MSb of the message description, the EOT field, always comes from
- * bit 127 of the instruction word"...which is bit 31 of this field.
- */
struct {
- GLuint function_control:19;
- GLuint header_present:1;
- GLuint response_length:5;
- GLuint msg_length:4;
+ GLuint src1_subreg_nr_high:1;
+ GLuint src1_reg_nr:8;
+ GLuint pad0:1;
+ GLuint src2_rep_ctrl:1;
+ GLuint src2_swizzle:8;
+ GLuint src2_subreg_nr:3;
+ GLuint src2_reg_nr:8;
GLuint pad1:2;
- GLuint end_of_thread:1;
- } generic_gen5;
+ } da3src;
GLint d;
GLuint ud;
} bits3;
};
+struct brw_compact_instruction {
+ struct {
+ unsigned opcode:7; /* 0- 6 */
+ unsigned debug_control:1; /* 7- 7 */
+ unsigned control_index:5; /* 8-12 */
+ unsigned data_type_index:5; /* 13-17 */
+ unsigned sub_reg_index:5; /* 18-22 */
+ unsigned acc_wr_control:1; /* 23-23 */
+ unsigned conditionalmod:4; /* 24-27 */
+ unsigned flag_subreg_nr:1; /* 28-28 */
+ unsigned cmpt_ctrl:1; /* 29-29 */
+ unsigned src0_index:2; /* 30-31 */
+ } dw0;
+
+ struct {
+ unsigned src0_index:3; /* 32-24 */
+ unsigned src1_index:5; /* 35-39 */
+ unsigned dst_reg_nr:8; /* 40-47 */
+ unsigned src0_reg_nr:8; /* 48-55 */
+ unsigned src1_reg_nr:8; /* 56-63 */
+ } dw1;
+};
#endif
projects / mesa.git / blobdiff