#ifndef BRW_STRUCTS_H
#define BRW_STRUCTS_H
-
-/** Number of general purpose registers (VS, WM, etc) */
-#define BRW_MAX_GRF 128
-
-/**
- * First GRF used for the MRF hack.
- *
- * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
- * haven't converted our compiler to be aware of this, so it asks for MRFs and
- * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
- * register allocators have to be careful of this to avoid corrupting the "MRF"s
- * with actual GRF allocations.
- */
-#define GEN7_MRF_HACK_START 112.
-
-/** Number of message register file registers */
-#define BRW_MAX_MRF 16
-
/* These seem to be passed around as function args, so it works out
* better to keep them as #defines:
*/
GLfloat pad1[4];
};
-/* volume 5c Shared Functions - 1.13.4.1.2 */
-struct gen7_surface_state
-{
- struct {
- GLuint cube_pos_z:1;
- GLuint cube_neg_z:1;
- GLuint cube_pos_y:1;
- GLuint cube_neg_y:1;
- GLuint cube_pos_x:1;
- GLuint cube_neg_x:1;
- GLuint pad2:2;
- GLuint render_cache_read_write:1;
- GLuint pad1:1;
- GLuint surface_array_spacing:1;
- GLuint vert_line_stride_ofs:1;
- GLuint vert_line_stride:1;
- GLuint tile_walk:1;
- GLuint tiled_surface:1;
- GLuint horizontal_alignment:1;
- GLuint vertical_alignment:2;
- GLuint surface_format:9; /**< BRW_SURFACEFORMAT_x */
- GLuint pad0:1;
- GLuint is_array:1;
- GLuint surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
- } ss0;
-
- struct {
- GLuint base_addr;
- } ss1;
-
- struct {
- GLuint width:14;
- GLuint pad1:2;
- GLuint height:14;
- GLuint pad0:2;
- } ss2;
-
- struct {
- GLuint pitch:18;
- GLuint pad:3;
- GLuint depth:11;
- } ss3;
-
- struct {
- GLuint multisample_position_palette_index:3;
- GLuint num_multisamples:3;
- GLuint multisampled_surface_storage_format:1;
- GLuint render_target_view_extent:11;
- GLuint min_array_elt:11;
- GLuint rotation:2;
- GLuint pad0:1;
- } ss4;
-
- struct {
- GLuint mip_count:4;
- GLuint min_lod:4;
- GLuint pad1:12;
- GLuint y_offset:4;
- GLuint pad0:1;
- GLuint x_offset:7;
- } ss5;
-
- union {
- GLuint raw_data;
- struct {
- GLuint y_offset_for_uv_plane:14;
- GLuint pad1:2;
- GLuint x_offset_for_uv_plane:14;
- GLuint pad0:2;
- } planar; /** Interpretation when Surface Format == PLANAR */
- struct {
- GLuint mcs_enable:1;
- GLuint append_counter_enable:1;
- GLuint pad:4;
- GLuint append_counter_address:26;
- } mcs_disabled; /** Interpretation when mcs_enable == 0 */
- struct {
- GLuint mcs_enable:1;
- GLuint pad:2;
- GLuint mcs_surface_pitch:9;
- GLuint mcs_base_address:20;
- } mcs_enabled; /** Interpretation when mcs_enable == 1 */
- } ss6;
-
- struct {
- GLuint resource_min_lod:12;
-
- /* Only on Haswell */
- GLuint pad0:4;
- GLuint shader_channel_select_a:3;
- GLuint shader_channel_select_b:3;
- GLuint shader_channel_select_g:3;
- GLuint shader_channel_select_r:3;
-
- GLuint alpha_clear_color:1;
- GLuint blue_clear_color:1;
- GLuint green_clear_color:1;
- GLuint red_clear_color:1;
- } ss7;
-};
-
-
struct brw_vertex_element_state
{
struct
GLuint access_mode:1;
GLuint mask_control:1;
GLuint dependency_control:2;
- GLuint compression_control:2; /* gen6: quater control */
+ GLuint compression_control:2; /* gen6: quarter control */
GLuint thread_control:2;
GLuint predicate_control:4;
GLuint predicate_inverse:1;
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
- GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_subreg_nr:5;
GLuint dest_reg_nr:8;
GLuint dest_horiz_stride:2;
GLuint src0_reg_type:3;
GLuint src1_reg_file:2; /* 0x00000c00 */
GLuint src1_reg_type:3; /* 0x00007000 */
- GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
GLuint dest_horiz_stride:2;
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
- GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLuint dest_subreg_nr:1;
GLuint dest_reg_nr:8;
GLuint dest_reg_type:3;
GLuint src0_reg_file:2;
GLuint src0_reg_type:3;
- GLuint pad0:6;
+ GLuint src1_reg_file:2;
+ GLuint src1_reg_type:3;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLint dest_indirect_offset:6;
GLuint dest_subreg_nr:3;
} branch_gen6;
struct {
- GLuint dest_reg_file:1;
+ GLuint dest_reg_file:1; /* gen6, not gen7+ */
GLuint flag_subreg_num:1;
- GLuint pad0:2;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad0:1;
GLuint src0_abs:1;
GLuint src0_negate:1;
GLuint src1_abs:1;
GLuint src1_negate:1;
GLuint src2_abs:1;
GLuint src2_negate:1;
- GLuint pad1:7;
+ GLuint src_type:2; /* gen7+ */
+ GLuint dst_type:2; /* gen7+ */
+ GLuint pad1:1;
+ GLuint nibctrl:1; /* gen7+ */
+ GLuint pad2:1;
GLuint dest_writemask:4;
GLuint dest_subreg_nr:3;
GLuint dest_reg_nr:8;
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
- GLuint pad:6;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad:5;
} da1;
struct
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
- GLuint pad:6;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad:5;
} ia1;
struct
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
- GLuint pad1:6;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad1:5;
} da16;
struct
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
- GLuint pad1:6;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad1:5;
} ia16;
/* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
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