i965: Set the destination horiz stride even for da16, as SNB seems to need it.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_structs.h

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 87d5c06cdc3acfe031e51e02cc8a646216064752..cdd2998627f9525c39f95bb6612ed5644edd4c58 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -278,7 +278,7 @@ struct brw_aa_line_parameters
    struct header header;
 
    struct {
-      GLuint aa_coverage_scope:8;
+      GLuint aa_coverage_slope:8;
       GLuint pad0:8;
       GLuint aa_coverage_bias:8;
       GLuint pad1:8;
@@ -925,7 +925,7 @@ struct brw_gs_unit_state
    struct
    {
       GLuint pad0:8;
-      GLuint rendering_enable:1; /* for IGDNG */
+      GLuint rendering_enable:1; /* for Ironlake */
       GLuint pad4:1;
       GLuint stats_enable:1; 
       GLuint nr_urb_entries:7; 
@@ -1035,7 +1035,7 @@ struct brw_wm_unit_state
    GLfloat global_depth_offset_constant;  
    GLfloat global_depth_offset_scale;   
    
-   /* for IGDNG only */
+   /* for Ironlake only */
    struct {
       GLuint pad0:1;
       GLuint grf_reg_count_1:3; 
@@ -1144,6 +1144,15 @@ struct brw_sf_viewport
    } scissor;
 };
 
+struct gen6_sf_viewport {
+   GLfloat m00;
+   GLfloat m11;
+   GLfloat m22;
+   GLfloat m30;
+   GLfloat m31;
+   GLfloat m32;
+};
+
 /* Documented in the subsystem/shared-functions/sampler chapter...
  */
 struct brw_surface_state
@@ -1296,13 +1305,14 @@ struct brw_instruction
       GLuint access_mode:1;
       GLuint mask_control:1;
       GLuint dependency_control:2;
-      GLuint compression_control:2;
+      GLuint compression_control:2; /* gen6: quater control */
       GLuint thread_control:2;
       GLuint predicate_control:4;
       GLuint predicate_inverse:1;
       GLuint execution_size:3;
       GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
-      GLuint pad0:2;
+      GLuint acc_wr_control:1;
+      GLuint cmpt_control:1;
       GLuint debug_control:1;
       GLuint saturate:1;
    } header;
@@ -1350,7 +1360,7 @@ struct brw_instruction
         GLuint dest_writemask:4;
         GLuint dest_subreg_nr:1;
         GLuint dest_reg_nr:8;
-        GLuint pad1:2;
+        GLuint dest_horiz_stride:2;
         GLuint dest_address_mode:1;
       } da16;
 
@@ -1364,7 +1374,7 @@ struct brw_instruction
         GLuint dest_writemask:4;
         GLint dest_indirect_offset:6;
         GLuint dest_subreg_nr:3;
-        GLuint pad1:2;
+        GLuint dest_horiz_stride:2;
         GLuint dest_address_mode:1;
       } ia16;
    } bits1;
@@ -1439,7 +1449,7 @@ struct brw_instruction
            GLuint end_of_thread:1;
            GLuint pad1:1;
            GLuint sfid:4;
-       } send_igdng;  /* for IGDNG only */
+       } send_gen5;  /* for Ironlake only */
 
    } bits2;
 
@@ -1540,7 +1550,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } math_igdng;
+      } math_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1576,7 +1586,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } sampler_igdng;
+      } sampler_gen5;
 
       struct brw_urb_immediate urb;
 
@@ -1594,7 +1604,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } urb_igdng;
+      } urb_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1619,7 +1629,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } dp_read_igdng;
+      } dp_read_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1646,10 +1656,38 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } dp_write_igdng;
+      } dp_write_gen5;
+
+      /* Sandybridge DP for sample cache, constant cache, render cache */
+      struct {
+        GLuint binding_table_index:8;
+        GLuint msg_control:5;
+        GLuint msg_type:3;
+        GLuint pad0:3;
+        GLuint header_present:1;
+        GLuint response_length:5;
+        GLuint msg_length:4;
+        GLuint pad1:2;
+        GLuint end_of_thread:1;
+      } dp_sampler_const_cache;
+
+      struct {
+        GLuint binding_table_index:8;
+        GLuint msg_control:3;
+        GLuint slot_group_select:1;
+        GLuint pixel_scoreboard_clear:1;
+        GLuint msg_type:4;
+        GLuint send_commit_msg:1;
+        GLuint pad0:1;
+        GLuint header_present:1;
+        GLuint response_length:5;
+        GLuint msg_length:4;
+        GLuint pad1:2;
+        GLuint end_of_thread:1;
+      } dp_render_cache;
 
       struct {
-        GLuint pad:16;
+        GLuint function_control:16;
         GLuint response_length:4;
         GLuint msg_length:4;
         GLuint msg_target:4;
@@ -1657,14 +1695,15 @@ struct brw_instruction
         GLuint end_of_thread:1;
       } generic;
 
+      /* Of this struct, only end_of_thread is not present for gen6. */
       struct {
-        GLuint pad:19;
+        GLuint function_control:19;
         GLuint header_present:1;
         GLuint response_length:5;
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } generic_igdng;
+      } generic_gen5;
 
       GLint d;
       GLuint ud;