intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_structs.h

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 75365e0756689e43af5bd44a1fd78d637769ad6d..e1ba5f838d465e1e7c74dc64d55df43340d2c683 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -33,14 +33,6 @@
 #ifndef BRW_STRUCTS_H
 #define BRW_STRUCTS_H
 
-/* These seem to be passed around as function args, so it works out
- * better to keep them as #defines:
- */
-#define BRW_FLUSH_READ_CACHE           0x1
-#define BRW_FLUSH_STATE_CACHE          0x2
-#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
-#define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
-
 struct brw_urb_fence
 {
    struct
@@ -774,29 +766,6 @@ struct gen7_sf_clip_viewport {
    GLfloat pad1[4];
 };
 
-struct brw_vertex_element_state
-{
-   struct
-   {
-      GLuint src_offset:11; 
-      GLuint pad:5;
-      GLuint src_format:9; 
-      GLuint pad0:1;
-      GLuint valid:1; 
-      GLuint vertex_buffer_index:5; 
-   } ve0;
-   
-   struct
-   {
-      GLuint dst_offset:8; 
-      GLuint pad:8;
-      GLuint vfcomponent3:4; 
-      GLuint vfcomponent2:4; 
-      GLuint vfcomponent1:4; 
-      GLuint vfcomponent0:4; 
-   } ve1;
-};
-
 struct brw_urb_immediate {
    GLuint opcode:4;
    GLuint offset:6;
@@ -824,7 +793,7 @@ struct brw_instruction
       GLuint access_mode:1;
       GLuint mask_control:1;
       GLuint dependency_control:2;
-      GLuint compression_control:2; /* gen6: quater control */
+      GLuint compression_control:2; /* gen6: quarter control */
       GLuint thread_control:2;
       GLuint predicate_control:4;
       GLuint predicate_inverse:1;
@@ -849,7 +818,7 @@ struct brw_instruction
         GLuint src0_reg_type:3;
         GLuint src1_reg_file:2;
         GLuint src1_reg_type:3;
-        GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
         GLuint dest_subreg_nr:5;
         GLuint dest_reg_nr:8;
         GLuint dest_horiz_stride:2;
@@ -864,7 +833,7 @@ struct brw_instruction
         GLuint src0_reg_type:3;
         GLuint src1_reg_file:2;        /* 0x00000c00 */
         GLuint src1_reg_type:3;        /* 0x00007000 */
-        GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
         GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
         GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
         GLuint dest_horiz_stride:2;
@@ -879,7 +848,7 @@ struct brw_instruction
         GLuint src0_reg_type:3;
         GLuint src1_reg_file:2;
         GLuint src1_reg_type:3;
-        GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
         GLuint dest_writemask:4;
         GLuint dest_subreg_nr:1;
         GLuint dest_reg_nr:8;
@@ -893,7 +862,9 @@ struct brw_instruction
         GLuint dest_reg_type:3;
         GLuint src0_reg_file:2;
         GLuint src0_reg_type:3;
-        GLuint pad0:6;
+         GLuint src1_reg_file:2;
+         GLuint src1_reg_type:3;
+         GLuint nibctrl:1; /* gen7+ */
         GLuint dest_writemask:4;
         GLint dest_indirect_offset:6;
         GLuint dest_subreg_nr:3;
@@ -914,16 +885,21 @@ struct brw_instruction
       } branch_gen6;
 
       struct {
-        GLuint dest_reg_file:1;
+         GLuint dest_reg_file:1; /* gen6, not gen7+ */
         GLuint flag_subreg_num:1;
-        GLuint pad0:2;
+         GLuint flag_reg_nr:1; /* gen7+ */
+         GLuint pad0:1;
         GLuint src0_abs:1;
         GLuint src0_negate:1;
         GLuint src1_abs:1;
         GLuint src1_negate:1;
         GLuint src2_abs:1;
         GLuint src2_negate:1;
-        GLuint pad1:7;
+         GLuint src_type:2; /* gen7+ */
+         GLuint dst_type:2; /* gen7+ */
+         GLuint pad1:1;
+         GLuint nibctrl:1; /* gen7+ */
+         GLuint pad2:1;
         GLuint dest_writemask:4;
         GLuint dest_subreg_nr:3;
         GLuint dest_reg_nr:8;
@@ -945,7 +921,7 @@ struct brw_instruction
         GLuint src0_width:3;
         GLuint src0_vert_stride:4;
         GLuint flag_subreg_nr:1;
-        GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
         GLuint pad:5;
       } da1;
 
@@ -960,7 +936,7 @@ struct brw_instruction
         GLuint src0_width:3;
         GLuint src0_vert_stride:4;
         GLuint flag_subreg_nr:1;
-        GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
         GLuint pad:5;
       } ia1;
 
@@ -978,7 +954,7 @@ struct brw_instruction
         GLuint pad0:1;
         GLuint src0_vert_stride:4;
         GLuint flag_subreg_nr:1;
-        GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
         GLuint pad1:5;
       } da16;
 
@@ -996,7 +972,7 @@ struct brw_instruction
         GLuint pad0:1;
         GLuint src0_vert_stride:4;
         GLuint flag_subreg_nr:1;
-        GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
         GLuint pad1:5;
       } ia16;
 
@@ -1382,10 +1358,10 @@ struct brw_instruction
       /**
        * Message for any of the Gen7 Data Port caches.
        *
-       * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
-       * Data Port Messages / Message Descriptor.  Once again, "Slot Group
+       * Most fields are defined in the Ivybridge PRM, Volume 4 Part 1,
+       * section 3.9.2.1.1 "Message Descriptor".  Once again, "Slot Group
        * Select" and "Last Render Target" are part of the 6-bit message
-       * control for Render Target Writes.
+       * control for Render Target Writes (section 3.9.11.2).
        */
       struct {
         GLuint binding_table_index:8;