intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_surface_formats.c

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index c378f02daf9f7404e37eea15d0007dcf12d14a3a..0d8d805621e8313717d75c853afd4b61f75d1cfa 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -527,13 +527,12 @@ brw_format_for_mesa_format(gl_format mesa_format)
 void
 brw_init_surface_formats(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    int gen;
    gl_format format;
 
-   gen = intel->gen * 10;
-   if (intel->is_g4x)
+   gen = brw->gen * 10;
+   if (brw->is_g4x)
       gen += 5;
 
    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
@@ -649,10 +648,9 @@ brw_init_surface_formats(struct brw_context *brw)
 }
 
 bool
-brw_render_target_supported(struct intel_context *intel,
+brw_render_target_supported(struct brw_context *brw,
                            struct gl_renderbuffer *rb)
 {
-   struct brw_context *brw = brw_context(&intel->ctx);
    gl_format format = rb->Format;
 
    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
@@ -671,7 +669,7 @@ brw_render_target_supported(struct intel_context *intel,
     */
    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
       /* Gen6: MSAA on >64 bit formats is unsupported. */
-      if (intel->gen <= 6)
+      if (brw->gen <= 6)
          return false;
 
       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
@@ -683,12 +681,12 @@ brw_render_target_supported(struct intel_context *intel,
 }
 
 GLuint
-translate_tex_format(struct intel_context *intel,
+translate_tex_format(struct brw_context *brw,
                      gl_format mesa_format,
                     GLenum depth_mode,
                     GLenum srgb_decode)
 {
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    if (srgb_decode == GL_SKIP_DECODE_EXT)
       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 
@@ -714,7 +712,7 @@ translate_tex_format(struct intel_context *intel,
       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 
    case MESA_FORMAT_SRGB_DXT1:
-      if (intel->gen == 4 && !intel->is_g4x) {
+      if (brw->gen == 4 && !brw->is_g4x) {
          /* Work around missing SRGB DXT1 support on original gen4 by just
           * skipping SRGB decode.  It's not worth not supporting sRGB in
           * general to prevent this.
@@ -729,3 +727,22 @@ translate_tex_format(struct intel_context *intel,
       return brw_format_for_mesa_format(mesa_format);
    }
 }
+
+/** Can HiZ be enabled on a depthbuffer of the given format? */
+bool
+brw_is_hiz_depth_format(struct brw_context *brw, gl_format format)
+{
+   if (!brw->has_hiz)
+      return false;
+
+   switch (format) {
+   case MESA_FORMAT_Z32_FLOAT:
+   case MESA_FORMAT_Z32_FLOAT_X24S8:
+   case MESA_FORMAT_X8_Z24:
+   case MESA_FORMAT_S8_Z24:
+   case MESA_FORMAT_Z16:
+      return true;
+   default:
+      return false;
+   }
+}