i965/skl: Break down SIMD16 3-source instructions when required.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_surface_formats.c

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 5907dd9419a73ee19e028790ab4de9f49c53980b..7261c01258427d4f431b334094d86068bf3900e7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -368,9 +368,12 @@ brw_format_for_mesa_format(mesa_format mesa_format)
       [MESA_FORMAT_BGR_SRGB8] = 0,
       [MESA_FORMAT_A8B8G8R8_SRGB] = 0,
       [MESA_FORMAT_B8G8R8A8_SRGB] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
+      [MESA_FORMAT_A8R8G8B8_SRGB] = 0,
       [MESA_FORMAT_R8G8B8A8_SRGB] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB,
+      [MESA_FORMAT_X8R8G8B8_SRGB] = 0,
       [MESA_FORMAT_L_SRGB8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
       [MESA_FORMAT_L8A8_SRGB] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
+      [MESA_FORMAT_A8L8_SRGB] = 0,
       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
@@ -454,7 +457,6 @@ brw_format_for_mesa_format(mesa_format mesa_format)
       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 
-      [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
       [MESA_FORMAT_R_SNORM8] = BRW_SURFACEFORMAT_R8_SNORM,
       [MESA_FORMAT_R8G8_SNORM] = BRW_SURFACEFORMAT_R8G8_SNORM,
       [MESA_FORMAT_X8B8G8R8_SNORM] = 0,
@@ -488,9 +490,15 @@ brw_format_for_mesa_format(mesa_format mesa_format)
       [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = BRW_SURFACEFORMAT_ETC2_RGB8_PTA,
       [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = BRW_SURFACEFORMAT_ETC2_SRGB8_PTA,
 
+      [MESA_FORMAT_BPTC_RGBA_UNORM] = BRW_SURFACEFORMAT_BC7_UNORM,
+      [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = BRW_SURFACEFORMAT_BC7_UNORM_SRGB,
+      [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = BRW_SURFACEFORMAT_BC6H_SF16,
+      [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = BRW_SURFACEFORMAT_BC6H_UF16,
+
       [MESA_FORMAT_A_SNORM8] = 0,
       [MESA_FORMAT_L_SNORM8] = 0,
       [MESA_FORMAT_L8A8_SNORM] = 0,
+      [MESA_FORMAT_A8L8_SNORM] = 0,
       [MESA_FORMAT_I_SNORM8] = 0,
       [MESA_FORMAT_A_SNORM16] = 0,
       [MESA_FORMAT_L_SNORM16] = 0,
@@ -510,7 +518,8 @@ brw_format_for_mesa_format(mesa_format mesa_format)
       [MESA_FORMAT_B4G4R4X4_UNORM] = 0,
       [MESA_FORMAT_B5G5R5X1_UNORM] = BRW_SURFACEFORMAT_B5G5R5X1_UNORM,
       [MESA_FORMAT_R8G8B8X8_SNORM] = 0,
-      [MESA_FORMAT_R8G8B8X8_SRGB] = 0,
+      [MESA_FORMAT_R8G8B8X8_SRGB] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB,
+      [MESA_FORMAT_X8B8G8R8_SRGB] = 0,
       [MESA_FORMAT_RGBX_UINT8] = 0,
       [MESA_FORMAT_RGBX_SINT8] = 0,
       [MESA_FORMAT_B10G10R10X2_UNORM] = BRW_SURFACEFORMAT_B10G10R10X2_UNORM,
@@ -586,6 +595,9 @@ brw_init_surface_formats(struct brw_context *brw)
       case BRW_SURFACEFORMAT_R8G8B8X8_UNORM:
          render = BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
          break;
+      case BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB:
+         render = BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
+         break;
       }
 
       rinfo = &surface_formats[render];
@@ -610,6 +622,8 @@ brw_init_surface_formats(struct brw_context *brw)
    brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true;
    brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true;
    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
+   if (brw->gen >= 8)
+      brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true;
 
    /* We remap depth formats to a supported texturing format in
     * translate_tex_format().
@@ -629,7 +643,12 @@ brw_init_surface_formats(struct brw_context *brw)
     *
     * Other speculation is that we may be hitting increased fragment shader
     * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
+    *
+    * With the PMA stall workaround in place, Z16 is faster than Z24, as it
+    * should be.
     */
+   if (brw->gen >= 8)
+      ctx->TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
 
    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
@@ -768,8 +787,7 @@ brw_depth_format(struct brw_context *brw, mesa_format format)
    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
       return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
    default:
-      assert(!"Unexpected depth format.");
-      return BRW_DEPTHFORMAT_D32_FLOAT;
+      unreachable("Unexpected depth format.");
    }
 }