struct brw_tess_eval_program *tep,
struct brw_tes_prog_key *key)
{
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct brw_compiler *compiler = brw->screen->compiler;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct brw_stage_state *stage_state = &brw->tes.base;
nir_shader *nir = tep->program.Base.nir;
struct brw_tes_prog_data prog_data;
* padding around uniform values below vec4 size, so the worst case is that
* every uniform is a float which gets padded to the size of a vec4.
*/
- struct gl_shader *tes = shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
+ struct gl_linked_shader *tes =
+ shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
int param_count = nir->num_uniforms / 4;
prog_data.base.base.param =
/* Scratch space is used for register spilling */
brw_alloc_stage_scratch(brw, stage_state,
prog_data.base.base.total_scratch,
- brw->max_ds_threads);
+ devinfo->max_ds_threads);
brw_upload_cache(&brw->cache, BRW_CACHE_TES_PROG,
key, sizeof(*key),
key.patch_inputs_read = per_patch_slots;
/* _NEW_TEXTURE */
- brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count,
- &key.tex);
+ brw_populate_sampler_prog_key_data(ctx, prog, &key.tex);
if (!brw_search_cache(&brw->cache, BRW_CACHE_TES_PROG,
&key, sizeof(key),