i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex.c

diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index 8df8a120a8196936715438e18fa5cf117577161a..2cb9aa6503adbf2c7434a40deaca3d41d465d678 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -1,6 +1,6 @@
 /*
  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
  develop this 3D driver.
 
  Permission is hereby granted, free of charge, to any person obtaining
@@ -26,7 +26,7 @@
  **********************************************************************/
  /*
   * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
+  *   Keith Whitwell <keithw@vmware.com>
   */
 
 
@@ -34,7 +34,6 @@
 #include "main/mtypes.h"
 #include "main/teximage.h"
 
-#include "intel_regions.h"
 #include "intel_tex.h"
 #include "brw_context.h"
 
@@ -46,11 +45,12 @@ void brw_validate_textures( struct brw_context *brw )
 {
    struct gl_context *ctx = &brw->ctx;
    int i;
+   int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
 
-   for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
+   for (i = 0; i <= maxEnabledUnit; i++) {
       struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 
-      if (texUnit->_ReallyEnabled) {
+      if (texUnit->_Current) {
         intel_finalize_mipmap_tree(brw, i);
       }
    }