Merge commit 'origin/master' into gallium-msaa

[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex_layout.c

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7f9b2535340bf8dbd939dbc87dae47303b253693..768ccfd79c432d2bd49875fd01db1a7c3b13f99c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -36,7 +36,6 @@
 #include "intel_tex_layout.h"
 #include "intel_context.h"
 #include "main/macros.h"
-#include "intel_chipset.h"
 
 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
 
@@ -49,73 +48,31 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
 
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      if (IS_IGDNG(intel->intelScreen->deviceID)) {
-          GLuint align_h = 2, align_w = 4;
+      if (intel->gen == 5) {
+          GLuint align_h = 2;
           GLuint level;
-          GLuint x = 0;
-          GLuint y = 0;
-          GLuint width = mt->width0;
-          GLuint height = mt->height0;
           GLuint qpitch = 0;
-          GLuint y_pitch = 0;
-
-          mt->pitch = mt->width0;
-          intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-          y_pitch = ALIGN(height, align_h);
-
-          if (mt->compressed) {
-              mt->pitch = ALIGN(mt->width0, align_w);
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
-          } else {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
-          }
-
-          if (mt->first_level != mt->last_level) {
-              GLuint mip1_width;
+         int h0, h1, q;
 
-              if (mt->compressed) {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + ALIGN(minify(minify(mt->width0)), align_w);
-              } else {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + minify(minify(mt->width0));
-              }
-
-              if (mip1_width > mt->pitch) {
-                  mt->pitch = mip1_width;
-              }
-          }
+         /* On Ironlake, cube maps are finally represented as just a series
+          * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
+          * by a pitch of qpitch rows, where qpitch is defined by the equation
+          * given in Volume 1 of the BSpec.
+          */
+         h0 = ALIGN(mt->height0, align_h);
+         h1 = ALIGN(minify(h0), align_h);
+         qpitch = (h0 + h1 + 11 * align_h);
+          if (mt->compressed)
+            qpitch /= 4;
 
-          mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
+         i945_miptree_layout_2d(intel, mt, tiling, 6);
 
           for (level = mt->first_level; level <= mt->last_level; level++) {
-              GLuint img_height;
-              GLuint nr_images = 6;
-              GLuint q = 0;
-
-              intel_miptree_set_level_info(mt, level, nr_images, x, y, width, 
-                                           height, 1);
-
-              for (q = 0; q < nr_images; q++)
-                  intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
-
-              if (mt->compressed)
-                  img_height = MAX2(1, height/4);
-              else
-                  img_height = ALIGN(height, align_h);
-
-              if (level == mt->first_level + 1) {
-                  x += ALIGN(width, align_w);
-              }
-              else {
-                  y += img_height;
-              }
-
-              width  = minify(width);
-              height = minify(height);
+            for (q = 0; q < 6; q++) {
+               intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
+            }
           }
+         mt->total_height = qpitch * 6;
 
           break;
       }
@@ -134,10 +91,10 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
       intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
 
       if (mt->compressed) {
-          mt->pitch = ALIGN(width, align_w);
+          mt->total_width = ALIGN(width, align_w);
           pack_y_pitch = (height + 3) / 4;
       } else {
-        mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+        mt->total_width = mt->width0;
         pack_y_pitch = ALIGN(mt->height0, align_h);
       }
 
@@ -181,7 +138,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
            if (pack_x_pitch > 4) {
               pack_x_pitch >>= 1;
               pack_x_nr <<= 1;
-              assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+              assert(pack_x_pitch * pack_x_nr <= mt->total_width);
            }
 
            if (pack_y_pitch > 2) {
@@ -191,18 +148,25 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
         }
 
       }
+      /* The 965's sampler lays cachelines out according to how accesses
+       * in the texture surfaces run, so they may be "vertical" through
+       * memory.  As a result, the docs say in Surface Padding Requirements:
+       * Sampling Engine Surfaces that two extra rows of padding are required.
+       * We don't know of similar requirements for pre-965, but given that
+       * those docs are silent on padding requirements in general, let's play
+       * it safe.
+       */
+      if (mt->target == GL_TEXTURE_CUBE_MAP)
+        mt->total_height += 2;
       break;
    }
 
    default:
-      i945_miptree_layout_2d(intel, mt, tiling);
+      i945_miptree_layout_2d(intel, mt, tiling, 1);
       break;
    }
-   DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
-               mt->pitch,
-               mt->total_height,
-               mt->cpp,
-               mt->pitch * mt->total_height * mt->cpp );
+   DBG("%s: %dx%dx%d\n", __FUNCTION__,
+       mt->total_width, mt->total_height, mt->cpp);
 
    return GL_TRUE;
 }