i965: Mostly fix glsl-max-varyings.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex_layout.c

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 67d8d96947ec54b007dba3f7c18b298888f3ae61..768ccfd79c432d2bd49875fd01db1a7c3b13f99c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -48,6 +48,35 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
 
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
+      if (intel->gen == 5) {
+          GLuint align_h = 2;
+          GLuint level;
+          GLuint qpitch = 0;
+         int h0, h1, q;
+
+         /* On Ironlake, cube maps are finally represented as just a series
+          * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
+          * by a pitch of qpitch rows, where qpitch is defined by the equation
+          * given in Volume 1 of the BSpec.
+          */
+         h0 = ALIGN(mt->height0, align_h);
+         h1 = ALIGN(minify(h0), align_h);
+         qpitch = (h0 + h1 + 11 * align_h);
+          if (mt->compressed)
+            qpitch /= 4;
+
+         i945_miptree_layout_2d(intel, mt, tiling, 6);
+
+          for (level = mt->first_level; level <= mt->last_level; level++) {
+            for (q = 0; q < 6; q++) {
+               intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
+            }
+          }
+         mt->total_height = qpitch * 6;
+
+          break;
+      }
+
    case GL_TEXTURE_3D: {
       GLuint width  = mt->width0;
       GLuint height = mt->height0;
@@ -59,13 +88,13 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
       GLuint align_w = 4;
 
       mt->total_height = 0;
+      intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
 
       if (mt->compressed) {
-          align_w = intel_compressed_alignment(mt->internal_format);
-          mt->pitch = ALIGN(width, align_w);
+          mt->total_width = ALIGN(width, align_w);
           pack_y_pitch = (height + 3) / 4;
       } else {
-        mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+        mt->total_width = mt->width0;
         pack_y_pitch = ALIGN(mt->height0, align_h);
       }
 
@@ -109,7 +138,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
            if (pack_x_pitch > 4) {
               pack_x_pitch >>= 1;
               pack_x_nr <<= 1;
-              assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+              assert(pack_x_pitch * pack_x_nr <= mt->total_width);
            }
 
            if (pack_y_pitch > 2) {
@@ -119,18 +148,25 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
         }
 
       }
+      /* The 965's sampler lays cachelines out according to how accesses
+       * in the texture surfaces run, so they may be "vertical" through
+       * memory.  As a result, the docs say in Surface Padding Requirements:
+       * Sampling Engine Surfaces that two extra rows of padding are required.
+       * We don't know of similar requirements for pre-965, but given that
+       * those docs are silent on padding requirements in general, let's play
+       * it safe.
+       */
+      if (mt->target == GL_TEXTURE_CUBE_MAP)
+        mt->total_height += 2;
       break;
    }
 
    default:
-      i945_miptree_layout_2d(intel, mt, tiling);
+      i945_miptree_layout_2d(intel, mt, tiling, 1);
       break;
    }
-   DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
-               mt->pitch,
-               mt->total_height,
-               mt->cpp,
-               mt->pitch * mt->total_height * mt->cpp );
+   DBG("%s: %dx%dx%d\n", __FUNCTION__,
+       mt->total_width, mt->total_height, mt->cpp);
 
    return GL_TRUE;
 }