#include "intel_tex_layout.h"
#include "intel_context.h"
#include "main/macros.h"
-#include "intel_chipset.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
- if (IS_IGDNG(intel->intelScreen->deviceID)) {
+ if (intel->gen == 5) {
GLuint align_h = 2, align_w = 4;
GLuint level;
GLuint x = 0;
GLuint qpitch = 0;
GLuint y_pitch = 0;
- mt->pitch = mt->width0;
+ mt->total_width = mt->width0;
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
y_pitch = ALIGN(height, align_h);
if (mt->compressed) {
- mt->pitch = ALIGN(mt->width0, align_w);
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
- } else {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
+ mt->total_width = ALIGN(mt->width0, align_w);
}
if (mt->first_level != mt->last_level) {
+ minify(minify(mt->width0));
}
- if (mip1_width > mt->pitch) {
- mt->pitch = mip1_width;
+ if (mip1_width > mt->total_width) {
+ mt->total_width = mip1_width;
}
}
- mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
+ if (mt->compressed) {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
+ mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
+ } else {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h);
+ mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
+ }
for (level = mt->first_level; level <= mt->last_level; level++) {
GLuint img_height;
height, 1);
for (q = 0; q < nr_images; q++)
- intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
+ intel_miptree_set_image_offset(mt, level, q,
+ x, y + q * qpitch);
if (mt->compressed)
img_height = MAX2(1, height/4);
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
if (mt->compressed) {
- mt->pitch = ALIGN(width, align_w);
+ mt->total_width = ALIGN(width, align_w);
pack_y_pitch = (height + 3) / 4;
} else {
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ mt->total_width = mt->width0;
pack_y_pitch = ALIGN(mt->height0, align_h);
}
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+ assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {
}
}
+ /* The 965's sampler lays cachelines out according to how accesses
+ * in the texture surfaces run, so they may be "vertical" through
+ * memory. As a result, the docs say in Surface Padding Requirements:
+ * Sampling Engine Surfaces that two extra rows of padding are required.
+ * We don't know of similar requirements for pre-965, but given that
+ * those docs are silent on padding requirements in general, let's play
+ * it safe.
+ */
+ if (mt->target == GL_TEXTURE_CUBE_MAP)
+ mt->total_height += 2;
break;
}
i945_miptree_layout_2d(intel, mt, tiling);
break;
}
- DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
- mt->pitch,
- mt->total_height,
- mt->cpp,
- mt->pitch * mt->total_height * mt->cpp );
+ DBG("%s: %dx%dx%d\n", __FUNCTION__,
+ mt->total_width, mt->total_height, mt->cpp);
return GL_TRUE;
}