static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
{
+ if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
+ return 16;
+
/**
- * From the "Alignment Unit Size" section of various specs, namely:
- * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
- * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
- * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
- * - BSpec (for Ivybridge and slight variations in separate stencil)
- *
* +----------------------------------------------------------------------+
* | | alignment unit width ("i") |
* | Surface Property |-----------------------------|
* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
*/
- if (_mesa_is_format_compressed(mt->format)) {
- /* The hardware alignment requirements for compressed textures
- * happen to match the block boundaries.
- */
- unsigned int i, j;
- _mesa_get_format_block_size(mt->format, &i, &j);
-
- /* On Gen9+ we can pick our own alignment for compressed textures but it
- * has to be a multiple of the block size. The minimum alignment we can
- * pick is 4 so we effectively have to align to 4 times the block
- * size
- */
- if (brw->gen >= 9)
- return i * 4;
- else
- return i;
- }
-
- if (mt->format == MESA_FORMAT_S_UINT8)
- return 8;
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
- if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
- return 16;
-
return 4;
}
static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
- mesa_format format, bool multisampled)
+ const struct intel_mipmap_tree *mt)
{
/**
- * From the "Alignment Unit Size" section of various specs, namely:
- * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
- * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
- * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
- * - BSpec (for Ivybridge and slight variations in separate stencil)
- *
* +----------------------------------------------------------------------+
* | | alignment unit height ("j") |
* | Surface Property |-----------------------------|
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
- if (_mesa_is_format_compressed(format))
- /* See comment above for the horizontal alignment */
- return brw->gen >= 9 ? 16 : 4;
-
- if (format == MESA_FORMAT_S_UINT8)
- return brw->gen >= 7 ? 8 : 4;
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
* should always be used, except for stencil buffers, which should be 8.
if (brw->gen >= 8)
return 4;
- if (multisampled)
+ if (mt->num_samples > 1)
return 4;
- GLenum base_format = _mesa_get_format_base_format(format);
+ GLenum base_format = _mesa_get_format_base_format(mt->format);
if (brw->gen >= 6 &&
(base_format == GL_DEPTH_COMPONENT ||
*
* VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
*/
- if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
+ if (base_format == GL_YCBCR_MESA || mt->format == MESA_FORMAT_RGB_FLOAT32)
return 2;
return 4;
/* When this layout is used the horizontal alignment is fixed at 64 and the
* hardware ignores the value given in the surface state
*/
- const unsigned int align_w = 64;
+ const unsigned int halign = 64;
mt->total_height = mt->physical_height0;
mt->total_width = 0;
intel_miptree_set_level_info(mt, level, x, 0, depth);
- img_width = ALIGN(width, align_w);
+ img_width = ALIGN(width, halign);
mt->total_width = MAX2(mt->total_width, x + img_width);
unsigned y = 0;
unsigned width = mt->physical_width0;
unsigned height = mt->physical_height0;
- unsigned depth = mt->physical_depth0; /* number of array layers. */
+ /* Number of layers of array texture or slices of 3d texture (gen9+). */
+ unsigned depth = mt->physical_depth0;
unsigned int bw, bh;
_mesa_get_format_block_size(mt->format, &bw, &bh);
mt->total_width = mt->physical_width0;
-
- if (mt->compressed) {
- mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
- }
+ mt->total_width = ALIGN_NPOT(mt->total_width, bw);
/* May need to adjust width to accommodate the placement of
* the 2nd mipmap. This occurs when the alignment
if (mt->first_level != mt->last_level) {
unsigned mip1_width;
- if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
- ALIGN(minify(mt->physical_width0, 2), bw);
- } else {
- mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
- minify(mt->physical_width0, 2);
- }
-
- if (mip1_width > mt->total_width) {
- mt->total_width = mip1_width;
- }
+ mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
+ ALIGN_NPOT(minify(mt->physical_width0, 2), bw);
+
+ if (mip1_width > mt->total_width)
+ mt->total_width = mip1_width;
}
+ mt->total_width /= bw;
mt->total_height = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
intel_miptree_set_level_info(mt, level, x, y, depth);
- img_height = ALIGN(height, mt->align_h);
- if (mt->compressed)
- img_height /= bh;
+ img_height = ALIGN_NPOT(height, mt->valign);
+ img_height /= bh;
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
/* Compact arrays with separated miplevels */
mt->total_height = MAX2(mt->total_height, y + img_height);
/* Layout_below: step right after second mipmap.
+ *
+ * For Sandy Bridge HiZ and stencil, we always step down.
*/
if (level == mt->first_level + 1) {
- x += ALIGN(width, mt->align_w);
+ x += ALIGN_NPOT(width, mt->halign) / bw;
} else {
y += img_height;
}
}
}
+static void
+brw_miptree_layout_gen6_hiz_stencil(struct intel_mipmap_tree *mt)
+{
+ unsigned x = 0;
+ unsigned y = 0;
+ unsigned width = mt->physical_width0;
+ unsigned height = mt->physical_height0;
+ /* Number of layers of array texture. */
+ unsigned depth = mt->physical_depth0;
+ unsigned tile_width, tile_height, bw, bh;
+
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ bw = bh = 1;
+ /* W-tiled */
+ tile_width = 64;
+ tile_height = 64;
+ } else {
+ assert(_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT ||
+ _mesa_get_format_base_format(mt->format) == GL_DEPTH_STENCIL);
+ /* Each 128-bit HiZ block corresponds to a region of of 8x4 depth
+ * samples. Each cache line in the Y-Tiled HiZ image contains 2x2 HiZ
+ * blocks. Therefore, each Y-tiled cache line corresponds to an 16x8
+ * region in the depth surface. Since we're representing it as
+ * RGBA_FLOAT32, the miptree calculations will think that each cache
+ * line is 1x4 pixels. Therefore, we need a scale-down factor of 16x2
+ * and a vertical alignment of 2.
+ */
+ mt->cpp = 16;
+ bw = 16;
+ bh = 2;
+ /* Y-tiled */
+ tile_width = 128 / mt->cpp;
+ tile_height = 32;
+ }
+
+ mt->total_width = 0;
+ mt->total_height = 0;
+
+ for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
+ intel_miptree_set_level_info(
+ mt, level, x, y,
+ mt->target == GL_TEXTURE_3D ? minify(depth, level) : depth);
+
+ const unsigned img_width = ALIGN(DIV_ROUND_UP(width, bw), mt->halign);
+ const unsigned img_height =
+ ALIGN(DIV_ROUND_UP(height, bh), mt->valign) * depth;
+
+ mt->total_width = MAX2(mt->total_width, x + img_width);
+ mt->total_height = MAX2(mt->total_height, y + img_height);
+
+ if (level == mt->first_level) {
+ y += ALIGN(img_height, tile_height);
+ } else {
+ x += ALIGN(img_width, tile_width);
+ }
+
+ /* We only minify the width. We want qpitch to match for all miplevels
+ * because the hardware doesn't know we aren't on LOD0.
+ */
+ width = minify(width, 1);
+ }
+}
+
unsigned
brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level)
{
- assert(brw->gen < 9);
-
- if (mt->target == GL_TEXTURE_3D ||
+ if ((brw->gen < 9 && mt->target == GL_TEXTURE_3D) ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
- return ALIGN(minify(mt->physical_width0, level), mt->align_w);
+ return ALIGN_NPOT(minify(mt->physical_width0, level), mt->halign);
} else {
return 0;
}
const struct intel_mipmap_tree *mt,
unsigned level)
{
+ assert(mt->array_layout != GEN6_HIZ_STENCIL || brw->gen == 6);
+
if (brw->gen >= 9) {
/* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
* effectively end up with a packed qpitch anyway whenever
} else if (mt->target == GL_TEXTURE_3D ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP) ||
mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- return ALIGN(minify(mt->physical_height0, level), mt->align_h);
+ return ALIGN_NPOT(minify(mt->physical_height0, level), mt->valign);
+
+ } else if (mt->array_layout == GEN6_HIZ_STENCIL) {
+ /* For HiZ and stencil on Sandy Bridge, we don't minify the height. */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ return ALIGN(mt->physical_height0, mt->valign);
+ } else {
+ /* HiZ has a vertical scale factor of 2. */
+ return ALIGN(DIV_ROUND_UP(mt->physical_height0, 2), mt->valign);
+ }
} else {
- const unsigned h0 = ALIGN(mt->physical_height0, mt->align_h);
- const unsigned h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
+ const unsigned h0 = ALIGN_NPOT(mt->physical_height0, mt->valign);
+ const unsigned h1 = ALIGN_NPOT(minify(mt->physical_height0, 1), mt->valign);
- return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h;
+ return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->valign;
}
}
mt->total_height += 2;
}
-static bool
-use_linear_1d_layout(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+bool
+gen9_use_linear_1d_layout(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
/* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
* horizontal line. This isn't done for depth/stencil buffers however
struct intel_mipmap_tree *mt)
{
unsigned height = mt->physical_height0;
- bool layout_1d = use_linear_1d_layout(brw, mt);
+ bool layout_1d = gen9_use_linear_1d_layout(brw, mt);
int physical_qpitch;
if (layout_1d)
gen9_miptree_layout_1d(mt);
+ else if (mt->array_layout == GEN6_HIZ_STENCIL)
+ brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned img_height;
- img_height = ALIGN(height, mt->align_h);
+ img_height = ALIGN_NPOT(height, mt->valign);
if (mt->compressed)
- img_height /= mt->align_h;
+ img_height /= mt->valign;
- for (int q = 0; q < mt->level[level].depth; q++) {
+ for (unsigned q = 0; q < mt->level[level].depth; q++) {
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
} else {
brw_miptree_layout_texture_3d(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
- unsigned yscale = mt->compressed ? 4 : 1;
-
mt->total_width = 0;
mt->total_height = 0;
unsigned ysum = 0;
+ unsigned bh, bw;
+
+ _mesa_get_format_block_size(mt->format, &bw, &bh);
+
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
unsigned WL = MAX2(mt->physical_width0 >> level, 1);
unsigned HL = MAX2(mt->physical_height0 >> level, 1);
unsigned DL = MAX2(mt->physical_depth0 >> level, 1);
- unsigned wL = ALIGN(WL, mt->align_w);
- unsigned hL = ALIGN(HL, mt->align_h);
+ unsigned wL = ALIGN_NPOT(WL, mt->halign);
+ unsigned hL = ALIGN_NPOT(HL, mt->valign);
if (mt->target == GL_TEXTURE_CUBE_MAP)
DL = 6;
unsigned x = (q % (1 << level)) * wL;
unsigned y = ysum + (q >> level) * hL;
- intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
- mt->total_width = MAX2(mt->total_width, x + wL);
- mt->total_height = MAX2(mt->total_height, (y + hL) / yscale);
+ intel_miptree_set_image_offset(mt, level, q, x / bw, y / bh);
+ mt->total_width = MAX2(mt->total_width, (x + wL) / bw);
+ mt->total_height = MAX2(mt->total_height, (y + hL) / bh);
}
ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
*/
static uint32_t
brw_miptree_choose_tiling(struct brw_context *brw,
- enum intel_miptree_tiling_mode requested,
- const struct intel_mipmap_tree *mt)
+ const struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
{
if (mt->format == MESA_FORMAT_S_UINT8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
return I915_TILING_NONE;
}
+ /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
+ assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
+
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
- switch (requested) {
- case INTEL_MIPTREE_TILING_ANY:
+ switch (layout_flags & MIPTREE_LAYOUT_TILING_ANY) {
+ case MIPTREE_LAYOUT_TILING_ANY:
break;
- case INTEL_MIPTREE_TILING_Y:
+ case MIPTREE_LAYOUT_TILING_Y:
return I915_TILING_Y;
- case INTEL_MIPTREE_TILING_NONE:
+ case MIPTREE_LAYOUT_TILING_NONE:
return I915_TILING_NONE;
}
if (minimum_pitch < 64)
return I915_TILING_NONE;
- if (ALIGN(minimum_pitch, 512) >= 32768 ||
- mt->total_width >= 32768 || mt->total_height >= 32768) {
+ if (ALIGN(minimum_pitch, 512) >= 32768) {
perf_debug("%dx%d miptree too large to blit, falling back to untiled",
mt->total_width, mt->total_height);
return I915_TILING_NONE;
* to know that ahead of time. And besides, since we use a vertical
* alignment of 4 as often as we can, this shouldn't happen very often.
*/
- if (brw->gen == 7 && mt->align_h == 2 &&
- brw->format_supported_as_render_target[mt->format]) {
+ if (brw->gen == 7 && mt->valign == 2 &&
+ brw->mesa_format_supports_render[mt->format]) {
return I915_TILING_X;
}
return I915_TILING_Y | I915_TILING_X;
}
-
-void
-brw_miptree_layout(struct brw_context *brw,
- bool for_bo,
- enum intel_miptree_tiling_mode requested,
- struct intel_mipmap_tree *mt)
+static void
+intel_miptree_set_total_width_height(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
- bool multisampled = mt->num_samples > 1;
- bool gen6_hiz_or_stencil = false;
-
- if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- const GLenum base_format = _mesa_get_format_base_format(mt->format);
- gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
- }
-
- if (gen6_hiz_or_stencil) {
- /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
- * hardware doesn't support multiple mip levels on stencil/hiz.
- *
- * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
- * "The hierarchical depth buffer does not support the LOD field"
- *
- * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
- * "The stencil depth buffer does not support the LOD field"
- */
- if (mt->format == MESA_FORMAT_S_UINT8) {
- /* Stencil uses W tiling, so we force W tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 64;
- mt->align_h = 64;
- } else {
- /* Depth uses Y tiling, so we force need Y tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 128 / mt->cpp;
- mt->align_h = 32;
- }
- } else {
- mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
- mt->align_h =
- intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
- }
-
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
break;
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
- if (use_linear_1d_layout(brw, mt))
+ if (gen9_use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
+ else if (mt->array_layout == GEN6_HIZ_STENCIL)
+ brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
break;
}
break;
}
+
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
+}
- if (!mt->total_width || !mt->total_height) {
- intel_miptree_release(&mt);
- return;
+static void
+intel_miptree_set_alignment(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
+{
+ /**
+ * From the "Alignment Unit Size" section of various specs, namely:
+ * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
+ * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
+ * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
+ * - BSpec (for Ivybridge and slight variations in separate stencil)
+ */
+
+ if (mt->array_layout == GEN6_HIZ_STENCIL) {
+ /* On gen6, we use GEN6_HIZ_STENCIL for stencil/hiz because the
+ * hardware doesn't support multiple mip levels on stencil/hiz.
+ *
+ * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
+ * "The hierarchical depth buffer does not support the LOD field"
+ *
+ * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
+ * "The stencil depth buffer does not support the LOD field"
+ */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ /* Stencil uses W tiling, so we force W tiling alignment for the
+ * ALL_SLICES_AT_EACH_LOD miptree layout.
+ */
+ mt->halign = 4;
+ mt->valign = 2;
+ assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
+ } else {
+ /* See brw_miptree_layout_gen6_hiz_stencil() */
+ mt->halign = 1;
+ mt->valign = 2;
+ }
+ } else if (mt->compressed) {
+ /* The hardware alignment requirements for compressed textures
+ * happen to match the block boundaries.
+ */
+ _mesa_get_format_block_size(mt->format, &mt->halign, &mt->valign);
+
+ /* On Gen9+ we can pick our own alignment for compressed textures but it
+ * has to be a multiple of the block size. The minimum alignment we can
+ * pick is 4 so we effectively have to align to 4 times the block
+ * size
+ */
+ if (brw->gen >= 9) {
+ mt->halign *= 4;
+ mt->valign *= 4;
+ }
+ } else if (mt->format == MESA_FORMAT_S_UINT8) {
+ mt->halign = 8;
+ mt->valign = brw->gen >= 7 ? 8 : 4;
+ } else {
+ mt->halign =
+ intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
+ mt->valign = intel_vertical_texture_alignment_unit(brw, mt);
}
+}
+
+bool
+brw_miptree_layout(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
+{
+ intel_miptree_set_alignment(brw, mt, layout_flags);
+ intel_miptree_set_total_width_height(brw, mt);
+
+ if (!mt->total_width || !mt->total_height)
+ return false;
/* On Gen9+ the alignment values are expressed in multiples of the block
* size
if (brw->gen >= 9) {
unsigned int i, j;
_mesa_get_format_block_size(mt->format, &i, &j);
- mt->align_w /= i;
- mt->align_h /= j;
+ mt->halign /= i;
+ mt->valign /= j;
}
- if (!for_bo)
- mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
+ if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
+ mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
+
+ return true;
}
projects / mesa.git / blobdiff