i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex_layout.c

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 0a46d1c403269e2e4a5e346fc7dd05e3b207dca0..e4e66b4219c2128fa343ad6d4f38987f33b32135 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -33,13 +33,13 @@
  */
 
 #include "intel_mipmap_tree.h"
-#include "intel_context.h"
+#include "brw_context.h"
 #include "main/macros.h"
 
 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
 
 static unsigned int
-intel_horizontal_texture_alignment_unit(struct intel_context *intel,
+intel_horizontal_texture_alignment_unit(struct brw_context *brw,
                                        gl_format format)
 {
    /**
@@ -78,22 +78,14 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel,
    if (format == MESA_FORMAT_S8)
       return 8;
 
-   /* The depth alignment requirements in the table above are for rendering to
-    * depth miplevels using the LOD control fields.  We don't use LOD control
-    * fields, and instead use page offsets plus intra-tile x/y offsets, which
-    * require that the low 3 bits are zero.  To reduce the number of x/y
-    * offset workaround blits we do, align the X to 8, which depth texturing
-    * can handle (sadly, it can't handle 8 in the Y direction).
-    */
-   if (intel->gen >= 7 &&
-       _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
+   if (brw->gen >= 7 && format == MESA_FORMAT_Z16)
       return 8;
 
    return 4;
 }
 
 static unsigned int
-intel_vertical_texture_alignment_unit(struct intel_context *intel,
+intel_vertical_texture_alignment_unit(struct brw_context *brw,
                                      gl_format format)
 {
    /**
@@ -125,11 +117,11 @@ intel_vertical_texture_alignment_unit(struct intel_context *intel,
       return 4;
 
    if (format == MESA_FORMAT_S8)
-      return intel->gen >= 7 ? 8 : 4;
+      return brw->gen >= 7 ? 8 : 4;
 
    GLenum base_format = _mesa_get_format_base_format(format);
 
-   if (intel->gen >= 6 &&
+   if (brw->gen >= 6 &&
        (base_format == GL_DEPTH_COMPONENT ||
        base_format == GL_DEPTH_STENCIL)) {
       return 4;
@@ -205,7 +197,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 }
 
 static void
-brw_miptree_layout_texture_array(struct intel_context *intel,
+brw_miptree_layout_texture_array(struct brw_context *brw,
                                 struct intel_mipmap_tree *mt)
 {
    unsigned qpitch = 0;
@@ -216,7 +208,7 @@ brw_miptree_layout_texture_array(struct intel_context *intel,
    if (mt->array_spacing_lod0)
       qpitch = h0;
    else
-      qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * mt->align_h);
+      qpitch = (h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h);
    if (mt->compressed)
       qpitch /= 4;
 
@@ -231,7 +223,7 @@ brw_miptree_layout_texture_array(struct intel_context *intel,
 }
 
 static void
-brw_miptree_layout_texture_3d(struct intel_context *intel,
+brw_miptree_layout_texture_3d(struct brw_context *brw,
                               struct intel_mipmap_tree *mt)
 {
    unsigned width  = mt->physical_width0;
@@ -309,39 +301,39 @@ brw_miptree_layout_texture_3d(struct intel_context *intel,
 }
 
 void
-brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
+brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
 {
-   mt->align_w = intel_horizontal_texture_alignment_unit(intel, mt->format);
-   mt->align_h = intel_vertical_texture_alignment_unit(intel, mt->format);
+   mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
+   mt->align_h = intel_vertical_texture_alignment_unit(brw, mt->format);
 
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      if (intel->gen == 4) {
+      if (brw->gen == 4) {
          /* Gen4 stores cube maps as 3D textures. */
          assert(mt->physical_depth0 == 6);
-         brw_miptree_layout_texture_3d(intel, mt);
+         brw_miptree_layout_texture_3d(brw, mt);
       } else {
          /* All other hardware stores cube maps as 2D arrays. */
-        brw_miptree_layout_texture_array(intel, mt);
+        brw_miptree_layout_texture_array(brw, mt);
       }
       break;
 
    case GL_TEXTURE_3D:
-      brw_miptree_layout_texture_3d(intel, mt);
+      brw_miptree_layout_texture_3d(brw, mt);
       break;
 
    case GL_TEXTURE_1D_ARRAY:
    case GL_TEXTURE_2D_ARRAY:
    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
    case GL_TEXTURE_CUBE_MAP_ARRAY:
-      brw_miptree_layout_texture_array(intel, mt);
+      brw_miptree_layout_texture_array(brw, mt);
       break;
 
    default:
       switch (mt->msaa_layout) {
       case INTEL_MSAA_LAYOUT_UMS:
       case INTEL_MSAA_LAYOUT_CMS:
-         brw_miptree_layout_texture_array(intel, mt);
+         brw_miptree_layout_texture_array(brw, mt);
          break;
       case INTEL_MSAA_LAYOUT_NONE:
       case INTEL_MSAA_LAYOUT_IMS: