Merge commit 'mesa_7_6_branch' into mesa_7_7_branch

[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex_layout.c

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1d2e953eb1ef173e84055a247ba90a6340c2fbfe..e59e52ed8612da84da15c1d99b3e34198d8531c1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -86,10 +86,10 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
           mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
 
           if (mt->compressed) {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
+              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
               mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
           } else {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
+              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h);
               mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
           }
 
@@ -102,7 +102,8 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
                                            height, 1);
 
               for (q = 0; q < nr_images; q++)
-                  intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
+                  intel_miptree_set_image_offset(mt, level, q,
+                                                x, y + q * qpitch);
 
               if (mt->compressed)
                   img_height = MAX2(1, height/4);
@@ -194,6 +195,16 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
         }
 
       }
+      /* The 965's sampler lays cachelines out according to how accesses
+       * in the texture surfaces run, so they may be "vertical" through
+       * memory.  As a result, the docs say in Surface Padding Requirements:
+       * Sampling Engine Surfaces that two extra rows of padding are required.
+       * We don't know of similar requirements for pre-965, but given that
+       * those docs are silent on padding requirements in general, let's play
+       * it safe.
+       */
+      if (mt->target == GL_TEXTURE_CUBE_MAP)
+        mt->total_height += 2;
       break;
    }