int i = 0;
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
switch(mt->target) {
case GL_TEXTURE_1D:
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 2:
mt->target != GL_TEXTURE_1D_ARRAY);
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)) ;
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ;
switch(mt->target) {
case GL_TEXTURE_2D:
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 4:
*/
static uint32_t
brw_miptree_choose_tiling(struct brw_context *brw,
- enum intel_miptree_tiling_mode requested,
- const struct intel_mipmap_tree *mt)
+ const struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
{
if (mt->format == MESA_FORMAT_S_UINT8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
return I915_TILING_NONE;
}
+ /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
+ assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
+
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
- switch (requested) {
- case INTEL_MIPTREE_TILING_ANY:
+ switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
+ case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
break;
- case INTEL_MIPTREE_TILING_Y:
+ case MIPTREE_LAYOUT_ALLOC_YTILED:
return I915_TILING_Y;
- case INTEL_MIPTREE_TILING_NONE:
+ case MIPTREE_LAYOUT_ALLOC_LINEAR:
return I915_TILING_NONE;
}
void
brw_miptree_layout(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- enum intel_miptree_tiling_mode requested,
uint32_t layout_flags)
{
- const unsigned bpp = mt->cpp * 8;
- /* Enable YF/YS tiling only for color surfaces because depth and
- * stencil surfaces are not supported in blitter using fast copy
- * blit and meta PBO upload, download paths. No other paths
- * currently support Yf/Ys tiled surfaces.
- * FINISHME: Remove this restriction once we have a tiled_memcpy()
- * path to do depth/stencil data upload/download to Yf/Ys tiled
- * surfaces.
- */
- const bool is_tr_mode_yf_ys_allowed =
- brw->gen >= 9 &&
- !(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
- !mt->compressed &&
- _mesa_is_format_color_format(mt->format) &&
- (requested == INTEL_MIPTREE_TILING_Y ||
- requested == INTEL_MIPTREE_TILING_ANY) &&
- (bpp && is_power_of_two(bpp)) &&
- /* FIXME: To avoid piglit regressions keep the Yf/Ys tiling
- * disabled at the moment.
- */
- false;
-
- /* Lower index (Yf) is the higher priority mode */
- const uint32_t tr_mode[3] = {INTEL_MIPTREE_TRMODE_YF,
- INTEL_MIPTREE_TRMODE_YS,
- INTEL_MIPTREE_TRMODE_NONE};
- int i = is_tr_mode_yf_ys_allowed ? 0 : ARRAY_SIZE(tr_mode) - 1;
-
- while (i < ARRAY_SIZE(tr_mode)) {
- if (brw->gen < 9)
- assert(tr_mode[i] == INTEL_MIPTREE_TRMODE_NONE);
- else
- assert(tr_mode[i] == INTEL_MIPTREE_TRMODE_YF ||
- tr_mode[i] == INTEL_MIPTREE_TRMODE_YS ||
- tr_mode[i] == INTEL_MIPTREE_TRMODE_NONE);
-
- mt->tr_mode = tr_mode[i];
- intel_miptree_set_alignment(brw, mt, layout_flags);
- intel_miptree_set_total_width_height(brw, mt);
-
- if (!mt->total_width || !mt->total_height) {
- intel_miptree_release(&mt);
- break;
- }
+ mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
- /* On Gen9+ the alignment values are expressed in multiples of the
- * block size.
- */
- if (brw->gen >= 9) {
- unsigned int i, j;
- _mesa_get_format_block_size(mt->format, &i, &j);
- mt->align_w /= i;
- mt->align_h /= j;
- }
+ intel_miptree_set_alignment(brw, mt, layout_flags);
+ intel_miptree_set_total_width_height(brw, mt);
- /* If there is already a BO, we cannot effect tiling modes */
- if (layout_flags & MIPTREE_LAYOUT_FOR_BO)
- break;
+ if (!mt->total_width || !mt->total_height) {
+ intel_miptree_release(&mt);
+ return;
+ }
- mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
- if (is_tr_mode_yf_ys_allowed) {
- unsigned int level = 0;
-
- if (mt->tiling == I915_TILING_Y ||
- mt->tiling == (I915_TILING_Y | I915_TILING_X) ||
- mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE) {
- /* FIXME: Don't allow YS tiling at the moment. Using 64KB tiling
- * for small textures might result in to memory wastage. Revisit
- * this condition when we have more information about the specific
- * cases where using YS over YF will be useful.
- */
- if (mt->tr_mode != INTEL_MIPTREE_TRMODE_YS)
- break;
- }
- /* Failed to use selected tr_mode. Free up the memory allocated
- * for miptree levels in intel_miptree_total_width_height().
- */
- for (level = mt->first_level; level <= mt->last_level; level++) {
- free(mt->level[level].slice);
- mt->level[level].slice = NULL;
- }
- }
- i++;
+ /* On Gen9+ the alignment values are expressed in multiples of the block
+ * size
+ */
+ if (brw->gen >= 9) {
+ unsigned int i, j;
+ _mesa_get_format_block_size(mt->format, &i, &j);
+ mt->align_w /= i;
+ mt->align_h /= j;
}
+
+ if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
+ mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
}
projects / mesa.git / blobdiff