int i = 0;
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
switch(mt->target) {
case GL_TEXTURE_1D:
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 2:
static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
{
+ if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
+ return 16;
+
/**
* From the "Alignment Unit Size" section of various specs, namely:
* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
- if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
- return 16;
-
return 4;
}
mt->target != GL_TEXTURE_1D_ARRAY);
/* Alignment computations below assume bpp >= 8 and a power of 2. */
- assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)) ;
+ assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ;
switch(mt->target) {
case GL_TEXTURE_2D:
ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
align_yf[i] : align_ys[i];
- assert(is_power_of_two(mt->num_samples));
+ assert(_mesa_is_pow_two(mt->num_samples));
switch (mt->num_samples) {
case 4:
mt->total_width = mt->physical_width0;
- if (mt->compressed) {
- mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
- }
+ if (mt->compressed)
+ mt->total_width = ALIGN(mt->total_width, bw);
/* May need to adjust width to accommodate the placement of
* the 2nd mipmap. This occurs when the alignment
mt->total_height += 2;
}
-static bool
-use_linear_1d_layout(struct brw_context *brw,
- struct intel_mipmap_tree *mt)
+bool
+gen9_use_linear_1d_layout(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
{
/* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
* horizontal line. This isn't done for depth/stencil buffers however
struct intel_mipmap_tree *mt)
{
unsigned height = mt->physical_height0;
- bool layout_1d = use_linear_1d_layout(brw, mt);
+ bool layout_1d = gen9_use_linear_1d_layout(brw, mt);
int physical_qpitch;
if (layout_1d)
*/
static uint32_t
brw_miptree_choose_tiling(struct brw_context *brw,
- enum intel_miptree_tiling_mode requested,
- const struct intel_mipmap_tree *mt)
+ const struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
{
if (mt->format == MESA_FORMAT_S_UINT8) {
/* The stencil buffer is W tiled. However, we request from the kernel a
return I915_TILING_NONE;
}
+ /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
+ assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
+
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
- switch (requested) {
- case INTEL_MIPTREE_TILING_ANY:
+ switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
+ case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
break;
- case INTEL_MIPTREE_TILING_Y:
+ case MIPTREE_LAYOUT_ALLOC_YTILED:
return I915_TILING_Y;
- case INTEL_MIPTREE_TILING_NONE:
+ case MIPTREE_LAYOUT_ALLOC_LINEAR:
return I915_TILING_NONE;
}
return I915_TILING_Y | I915_TILING_X;
}
-
-void
-brw_miptree_layout(struct brw_context *brw,
- bool for_bo,
- enum intel_miptree_tiling_mode requested,
- struct intel_mipmap_tree *mt)
+static void
+intel_miptree_set_total_width_height(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
- bool gen6_hiz_or_stencil = false;
-
- mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
-
- if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- const GLenum base_format = _mesa_get_format_base_format(mt->format);
- gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
- }
-
- if (gen6_hiz_or_stencil) {
- /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
- * hardware doesn't support multiple mip levels on stencil/hiz.
- *
- * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
- * "The hierarchical depth buffer does not support the LOD field"
- *
- * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
- * "The stencil depth buffer does not support the LOD field"
- */
- if (mt->format == MESA_FORMAT_S_UINT8) {
- /* Stencil uses W tiling, so we force W tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 64;
- mt->align_h = 64;
- } else {
- /* Depth uses Y tiling, so we force need Y tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 128 / mt->cpp;
- mt->align_h = 32;
- }
- } else {
- mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
- mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
- }
-
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
break;
case INTEL_MSAA_LAYOUT_NONE:
case INTEL_MSAA_LAYOUT_IMS:
- if (use_linear_1d_layout(brw, mt))
+ if (gen9_use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
else
brw_miptree_layout_2d(mt);
}
break;
}
+
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
+}
+
+static void
+intel_miptree_set_alignment(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
+{
+ bool gen6_hiz_or_stencil = false;
+
+ if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+ const GLenum base_format = _mesa_get_format_base_format(mt->format);
+ gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
+ }
+
+ if (gen6_hiz_or_stencil) {
+ /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
+ * hardware doesn't support multiple mip levels on stencil/hiz.
+ *
+ * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
+ * "The hierarchical depth buffer does not support the LOD field"
+ *
+ * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
+ * "The stencil depth buffer does not support the LOD field"
+ */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ /* Stencil uses W tiling, so we force W tiling alignment for the
+ * ALL_SLICES_AT_EACH_LOD miptree layout.
+ */
+ mt->align_w = 64;
+ mt->align_h = 64;
+ assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
+ } else {
+ /* Depth uses Y tiling, so we force need Y tiling alignment for the
+ * ALL_SLICES_AT_EACH_LOD miptree layout.
+ */
+ mt->align_w = 128 / mt->cpp;
+ mt->align_h = 32;
+ }
+ } else {
+ mt->align_w =
+ intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
+ mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
+ }
+}
+
+void
+brw_miptree_layout(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layout_flags)
+{
+ mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+
+ intel_miptree_set_alignment(brw, mt, layout_flags);
+ intel_miptree_set_total_width_height(brw, mt);
if (!mt->total_width || !mt->total_height) {
intel_miptree_release(&mt);
mt->align_h /= j;
}
- if (!for_bo)
- mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
+ if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
+ mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
}
projects / mesa.git / blobdiff