i965/nir: Do not scalarize phis in non-scalar setups
[mesa.git] / src / mesa / drivers / dri / i965 / brw_urb.c
index 06aab6cdc278aa488bbc08256b1c2af845042e11..6078c3810d45abec4f4b2c0a0f77404bc8bd5257 100644 (file)
@@ -1,6 +1,6 @@
 /*
  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
  develop this 3D driver.
 
  Permission is hereby granted, free of charge, to any person obtaining
@@ -26,7 +26,7 @@
  **********************************************************************/
  /*
   * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
+  *   Keith Whitwell <keithw@vmware.com>
   */
 
 
@@ -185,25 +185,26 @@ static void recalculate_urb_fence( struct brw_context *brw )
             * entries and the values for minimum nr of entries
             * provided above.
             */
-           printf("couldn't calculate URB layout!\n");
+           fprintf(stderr, "couldn't calculate URB layout!\n");
            exit(1);
         }
        
         if (unlikely(INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF)))
-           printf("URB CONSTRAINED\n");
+           fprintf(stderr, "URB CONSTRAINED\n");
       }
 
 done:
       if (unlikely(INTEL_DEBUG & DEBUG_URB))
-        printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
-                     brw->urb.vs_start,
-                     brw->urb.gs_start,
-                     brw->urb.clip_start,
-                     brw->urb.sf_start,
-                     brw->urb.cs_start,
-                     brw->urb.size);
-
-      brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
+        fprintf(stderr,
+                 "URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
+                 brw->urb.vs_start,
+                 brw->urb.gs_start,
+                 brw->urb.clip_start,
+                 brw->urb.sf_start,
+                 brw->urb.cs_start,
+                 brw->urb.size);
+
+      brw->ctx.NewDriverState |= BRW_NEW_URB_FENCE;
    }
 }
 
@@ -211,9 +212,9 @@ done:
 const struct brw_tracked_state brw_recalculate_urb_fence = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_CURBE_OFFSETS,
-      .cache = (CACHE_NEW_VS_PROG |
-               CACHE_NEW_SF_PROG)
+      .brw = BRW_NEW_CURBE_OFFSETS |
+             BRW_NEW_SF_PROG_DATA |
+             BRW_NEW_VS_PROG_DATA,
    },
    .emit = recalculate_urb_fence
 };
@@ -248,10 +249,10 @@ void brw_upload_urb_fence(struct brw_context *brw)
    uf.bits1.cs_fence  = brw->urb.size;
 
    /* erratum: URB_FENCE must not cross a 64byte cacheline */
-   if ((brw->batch.used & 15) > 12) {
-      int pad = 16 - (brw->batch.used & 15);
+   if ((USED_BATCH(brw->batch) & 15) > 12) {
+      int pad = 16 - (USED_BATCH(brw->batch) & 15);
       do
-        brw->batch.map[brw->batch.used++] = MI_NOOP;
+         *brw->batch.map_next++ = MI_NOOP;
       while (--pad);
    }