#include "brw_cfg.h"
#include "brw_vs.h"
#include "brw_nir.h"
+#include "brw_vec4_builder.h"
#include "brw_vec4_live_variables.h"
#include "brw_dead_control_flow.h"
-
-extern "C" {
-#include "main/macros.h"
-#include "main/shaderobj.h"
-#include "program/prog_print.h"
#include "program/prog_parameter.h"
-}
-#include "main/context.h"
#define MAX_INSTRUCTION (1 << 30)
this->file = BAD_FILE;
}
-src_reg::src_reg(register_file file, int reg, const glsl_type *type)
+src_reg::src_reg(enum brw_reg_file file, int nr, const glsl_type *type)
{
init();
this->file = file;
- this->reg = reg;
+ this->nr = nr;
if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
this->swizzle = brw_swizzle_for_size(type->vector_elements);
else
init();
}
-src_reg::src_reg(float f)
-{
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_F;
- this->fixed_hw_reg.dw1.f = f;
-}
-
-src_reg::src_reg(uint32_t u)
-{
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_UD;
- this->fixed_hw_reg.dw1.ud = u;
-}
-
-src_reg::src_reg(int32_t i)
-{
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_D;
- this->fixed_hw_reg.dw1.d = i;
-}
-
-src_reg::src_reg(uint8_t vf[4])
-{
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_VF;
- memcpy(&this->fixed_hw_reg.dw1.ud, vf, sizeof(unsigned));
-}
-
-src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
-{
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_VF;
- this->fixed_hw_reg.dw1.ud = (vf0 << 0) |
- (vf1 << 8) |
- (vf2 << 16) |
- (vf3 << 24);
-}
-
-src_reg::src_reg(struct brw_reg reg)
+src_reg::src_reg(struct ::brw_reg reg) :
+ backend_reg(reg)
{
- init();
-
- this->file = HW_REG;
- this->fixed_hw_reg = reg;
- this->type = reg.type;
+ this->reg_offset = 0;
+ this->reladdr = NULL;
}
-src_reg::src_reg(const dst_reg ®)
+src_reg::src_reg(const dst_reg ®) :
+ backend_reg(reg)
{
- init();
-
- this->file = reg.file;
- this->reg = reg.reg;
- this->reg_offset = reg.reg_offset;
- this->type = reg.type;
this->reladdr = reg.reladdr;
- this->fixed_hw_reg = reg.fixed_hw_reg;
this->swizzle = brw_swizzle_for_mask(reg.writemask);
}
init();
}
-dst_reg::dst_reg(register_file file, int reg)
+dst_reg::dst_reg(enum brw_reg_file file, int nr)
{
init();
this->file = file;
- this->reg = reg;
+ this->nr = nr;
}
-dst_reg::dst_reg(register_file file, int reg, const glsl_type *type,
+dst_reg::dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
unsigned writemask)
{
init();
this->file = file;
- this->reg = reg;
+ this->nr = nr;
this->type = brw_type_for_base_type(type);
this->writemask = writemask;
}
-dst_reg::dst_reg(register_file file, int reg, brw_reg_type type,
+dst_reg::dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
unsigned writemask)
{
init();
this->file = file;
- this->reg = reg;
+ this->nr = nr;
this->type = type;
this->writemask = writemask;
}
-dst_reg::dst_reg(struct brw_reg reg)
+dst_reg::dst_reg(struct ::brw_reg reg) :
+ backend_reg(reg)
{
- init();
-
- this->file = HW_REG;
- this->fixed_hw_reg = reg;
- this->type = reg.type;
+ this->reg_offset = 0;
+ this->reladdr = NULL;
}
-dst_reg::dst_reg(const src_reg ®)
+dst_reg::dst_reg(const src_reg ®) :
+ backend_reg(reg)
{
- init();
-
- this->file = reg.file;
- this->reg = reg.reg;
- this->reg_offset = reg.reg_offset;
- this->type = reg.type;
this->writemask = brw_mask_for_swizzle(reg.swizzle);
this->reladdr = reg.reladdr;
- this->fixed_hw_reg = reg.fixed_hw_reg;
}
bool
dst_reg::equals(const dst_reg &r) const
{
- return (file == r.file &&
- reg == r.reg &&
- reg_offset == r.reg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
- writemask == r.writemask &&
+ return (this->backend_reg::equals(r) &&
(reladdr == r.reladdr ||
- (reladdr && r.reladdr && reladdr->equals(*r.reladdr))) &&
- ((file != HW_REG && file != IMM) ||
- memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
- sizeof(fixed_hw_reg)) == 0));
+ (reladdr && r.reladdr && reladdr->equals(*r.reladdr))));
}
bool
case SHADER_OPCODE_TYPED_ATOMIC:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
+ case VEC4_OPCODE_URB_READ:
+ case TCS_OPCODE_URB_WRITE:
+ case TCS_OPCODE_RELEASE_INPUT:
+ case SHADER_OPCODE_BARRIER:
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * Returns true if this instruction's sources and destinations cannot
+ * safely be the same register.
+ *
+ * In most cases, a register can be written over safely by the same
+ * instruction that is its last use. For a single instruction, the
+ * sources are dereferenced before writing of the destination starts
+ * (naturally).
+ *
+ * However, there are a few cases where this can be problematic:
+ *
+ * - Virtual opcodes that translate to multiple instructions in the
+ * code generator: if src == dst and one instruction writes the
+ * destination before a later instruction reads the source, then
+ * src will have been clobbered.
+ *
+ * The register allocator uses this information to set up conflicts between
+ * GRF sources and the destination.
+ */
+bool
+vec4_instruction::has_source_and_destination_hazard() const
+{
+ switch (opcode) {
+ case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
+ case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
+ case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
return true;
default:
return false;
case SHADER_OPCODE_TYPED_ATOMIC:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
+ case TCS_OPCODE_URB_WRITE:
return arg == 0 ? mlen : 1;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
return true;
}
+bool
+vec4_instruction::can_do_writemask(const struct brw_device_info *devinfo)
+{
+ switch (opcode) {
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ case VS_OPCODE_PULL_CONSTANT_LOAD:
+ case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
+ case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
+ case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
+ case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
+ case TES_OPCODE_CREATE_INPUT_READ_HEADER:
+ case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
+ case VEC4_OPCODE_URB_READ:
+ case SHADER_OPCODE_MOV_INDIRECT:
+ return false;
+ default:
+ /* The MATH instruction on Gen6 only executes in align1 mode, which does
+ * not support writemasking.
+ */
+ if (devinfo->gen == 6 && is_math())
+ return false;
+
+ if (is_tex())
+ return false;
+
+ return true;
+ }
+}
+
bool
vec4_instruction::can_change_types() const
{
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
+ case TCS_OPCODE_THREAD_END:
return 2;
case VS_OPCODE_URB_WRITE:
return 1;
return 0;
case GS_OPCODE_FF_SYNC:
return 1;
+ case TCS_OPCODE_URB_WRITE:
+ return 0;
case SHADER_OPCODE_SHADER_TIME_ADD:
return 0;
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_CMS:
+ case SHADER_OPCODE_TXF_CMS_W:
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
bool
src_reg::equals(const src_reg &r) const
{
- return (file == r.file &&
- reg == r.reg &&
- reg_offset == r.reg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
- swizzle == r.swizzle &&
- !reladdr && !r.reladdr &&
- memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
- sizeof(fixed_hw_reg)) == 0);
+ return (this->backend_reg::equals(r) &&
+ !reladdr && !r.reladdr);
}
bool
{
bool progress = false;
- int last_reg = -1, last_reg_offset = -1;
- enum register_file last_reg_file = BAD_FILE;
+ foreach_block(block, cfg) {
+ int last_reg = -1, last_reg_offset = -1;
+ enum brw_reg_file last_reg_file = BAD_FILE;
- int remaining_channels = 0;
- uint8_t imm[4];
- int inst_count = 0;
- vec4_instruction *imm_inst[4];
+ uint8_t imm[4] = { 0 };
+ int inst_count = 0;
+ vec4_instruction *imm_inst[4];
+ unsigned writemask = 0;
+ enum brw_reg_type dest_type = BRW_REGISTER_TYPE_F;
- foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- if (last_reg != inst->dst.reg ||
- last_reg_offset != inst->dst.reg_offset ||
- last_reg_file != inst->dst.file) {
- last_reg = inst->dst.reg;
- last_reg_offset = inst->dst.reg_offset;
- last_reg_file = inst->dst.file;
- remaining_channels = WRITEMASK_XYZW;
-
- inst_count = 0;
- }
+ foreach_inst_in_block_safe(vec4_instruction, inst, block) {
+ int vf = -1;
+ enum brw_reg_type need_type;
- if (inst->opcode != BRW_OPCODE_MOV ||
- inst->dst.writemask == WRITEMASK_XYZW ||
- inst->src[0].file != IMM)
- continue;
+ /* Look for unconditional MOVs from an immediate with a partial
+ * writemask. Skip type-conversion MOVs other than integer 0,
+ * where the type doesn't matter. See if the immediate can be
+ * represented as a VF.
+ */
+ if (inst->opcode == BRW_OPCODE_MOV &&
+ inst->src[0].file == IMM &&
+ inst->predicate == BRW_PREDICATE_NONE &&
+ inst->dst.writemask != WRITEMASK_XYZW &&
+ (inst->src[0].type == inst->dst.type || inst->src[0].d == 0)) {
+
+ vf = brw_float_to_vf(inst->src[0].d);
+ need_type = BRW_REGISTER_TYPE_D;
+
+ if (vf == -1) {
+ vf = brw_float_to_vf(inst->src[0].f);
+ need_type = BRW_REGISTER_TYPE_F;
+ }
+ } else {
+ last_reg = -1;
+ }
- int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.dw1.f);
- if (vf == -1)
- continue;
+ /* If this wasn't a MOV, or the destination register doesn't match,
+ * or we have to switch destination types, then this breaks our
+ * sequence. Combine anything we've accumulated so far.
+ */
+ if (last_reg != inst->dst.nr ||
+ last_reg_offset != inst->dst.reg_offset ||
+ last_reg_file != inst->dst.file ||
+ (vf > 0 && dest_type != need_type)) {
+
+ if (inst_count > 1) {
+ unsigned vf;
+ memcpy(&vf, imm, sizeof(vf));
+ vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf));
+ mov->dst.type = dest_type;
+ mov->dst.writemask = writemask;
+ inst->insert_before(block, mov);
+
+ for (int i = 0; i < inst_count; i++) {
+ imm_inst[i]->remove(block);
+ }
- if ((inst->dst.writemask & WRITEMASK_X) != 0)
- imm[0] = vf;
- if ((inst->dst.writemask & WRITEMASK_Y) != 0)
- imm[1] = vf;
- if ((inst->dst.writemask & WRITEMASK_Z) != 0)
- imm[2] = vf;
- if ((inst->dst.writemask & WRITEMASK_W) != 0)
- imm[3] = vf;
-
- imm_inst[inst_count++] = inst;
-
- remaining_channels &= ~inst->dst.writemask;
- if (remaining_channels == 0) {
- vec4_instruction *mov = MOV(inst->dst, imm);
- mov->dst.type = BRW_REGISTER_TYPE_F;
- mov->dst.writemask = WRITEMASK_XYZW;
- inst->insert_after(block, mov);
- last_reg = -1;
-
- for (int i = 0; i < inst_count; i++) {
- imm_inst[i]->remove(block);
+ progress = true;
+ }
+
+ inst_count = 0;
+ last_reg = -1;
+ writemask = 0;
+ dest_type = BRW_REGISTER_TYPE_F;
+
+ for (int i = 0; i < 4; i++) {
+ imm[i] = 0;
+ }
+ }
+
+ /* Record this instruction's value (if it was representable). */
+ if (vf != -1) {
+ if ((inst->dst.writemask & WRITEMASK_X) != 0)
+ imm[0] = vf;
+ if ((inst->dst.writemask & WRITEMASK_Y) != 0)
+ imm[1] = vf;
+ if ((inst->dst.writemask & WRITEMASK_Z) != 0)
+ imm[2] = vf;
+ if ((inst->dst.writemask & WRITEMASK_W) != 0)
+ imm[3] = vf;
+
+ writemask |= inst->dst.writemask;
+ imm_inst[inst_count++] = inst;
+
+ last_reg = inst->dst.nr;
+ last_reg_offset = inst->dst.reg_offset;
+ last_reg_file = inst->dst.file;
+ if (vf > 0)
+ dest_type = need_type;
}
- progress = true;
}
}
bool progress = false;
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG ||
+ if (inst->dst.file == BAD_FILE ||
+ inst->dst.file == ARF ||
+ inst->dst.file == FIXED_GRF ||
inst->is_send_from_grf())
continue;
/* Update sources' swizzles. */
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file != GRF &&
+ if (inst->src[i].file != VGRF &&
inst->src[i].file != ATTR &&
inst->src[i].file != UNIFORM)
continue;
/* Prior to this, uniforms have been in an array sized according to
* the number of vector uniforms present, sparsely filled (so an
* aggregate results in reg indices being skipped over). Now we're
- * going to cut those aggregates up so each .reg index is one
+ * going to cut those aggregates up so each .nr index is one
* vector. The goal is to make elimination of unused uniform
* components easier later.
*/
assert(!inst->src[i].reladdr);
- inst->src[i].reg += inst->src[i].reg_offset;
+ inst->src[i].nr += inst->src[i].reg_offset;
inst->src[i].reg_offset = 0;
}
}
-
- /* Update that everything is now vector-sized. */
- for (int i = 0; i < this->uniforms; i++) {
- this->uniform_size[i] = 1;
- }
}
void
if (inst->src[i].file != UNIFORM)
continue;
- int reg = inst->src[i].reg;
+ int reg = inst->src[i].nr;
for (int c = 0; c < 4; c++) {
if (!(readmask & (1 << c)))
continue;
BRW_GET_SWZ(inst->src[i].swizzle, c) + 1);
}
}
+
+ if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT &&
+ inst->src[0].file == UNIFORM) {
+ assert(inst->src[2].file == BRW_IMMEDIATE_VALUE);
+ assert(inst->src[0].subnr == 0);
+
+ unsigned bytes_read = inst->src[2].ud;
+ assert(bytes_read % 4 == 0);
+ unsigned vec4s_read = DIV_ROUND_UP(bytes_read, 16);
+
+ /* We just mark every register touched by a MOV_INDIRECT as being
+ * fully used. This ensures that it doesn't broken up piecewise by
+ * the next part of our packing algorithm.
+ */
+ int reg = inst->src[0].nr;
+ for (unsigned i = 0; i < vec4s_read; i++)
+ chans_used[reg + i] = 4;
+ }
}
int new_uniform_count = 0;
* push constants.
*/
for (int src = 0; src < uniforms; src++) {
- assert(src < uniform_array_size);
int size = chans_used[src];
if (size == 0)
/* Now, update the instructions for our repacked uniforms. */
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (int i = 0 ; i < 3; i++) {
- int src = inst->src[i].reg;
+ int src = inst->src[i].nr;
if (inst->src[i].file != UNIFORM)
continue;
- inst->src[i].reg = new_loc[src];
+ inst->src[i].nr = new_loc[src];
inst->src[i].swizzle += BRW_SWIZZLE4(new_chan[src], new_chan[src],
new_chan[src], new_chan[src]);
}
assert(!"unimplemented: saturate mixed types");
if (brw_saturate_immediate(inst->dst.type,
- &inst->src[0].fixed_hw_reg)) {
+ &inst->src[0].as_brw_reg())) {
inst->saturate = false;
progress = true;
}
inst->opcode = BRW_OPCODE_MOV;
switch (inst->src[0].type) {
case BRW_REGISTER_TYPE_F:
- inst->src[0] = src_reg(0.0f);
+ inst->src[0] = brw_imm_f(0.0f);
break;
case BRW_REGISTER_TYPE_D:
- inst->src[0] = src_reg(0);
+ inst->src[0] = brw_imm_d(0);
break;
case BRW_REGISTER_TYPE_UD:
- inst->src[0] = src_reg(0u);
+ inst->src[0] = brw_imm_ud(0u);
break;
default:
unreachable("not reached");
break;
}
break;
- case SHADER_OPCODE_RCP: {
- vec4_instruction *prev = (vec4_instruction *)inst->prev;
- if (prev->opcode == SHADER_OPCODE_SQRT) {
- if (inst->src[0].equals(src_reg(prev->dst))) {
- inst->opcode = SHADER_OPCODE_RSQ;
- inst->src[0] = prev->src[0];
- progress = true;
- }
- }
- break;
- }
case SHADER_OPCODE_BROADCAST:
if (is_uniform(inst->src[0]) ||
inst->src[1].is_zero()) {
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
for (int i = 0 ; i < 3; i++) {
if (inst->src[i].file != UNIFORM ||
- pull_constant_loc[inst->src[i].reg] == -1)
+ pull_constant_loc[inst->src[i].nr] == -1)
continue;
- int uniform = inst->src[i].reg;
+ int uniform = inst->src[i].nr;
dst_reg temp = dst_reg(this, glsl_type::vec4_type);
emit_pull_constant_load(block, inst, temp, inst->src[i],
- pull_constant_loc[uniform]);
+ pull_constant_loc[uniform], src_reg());
inst->src[i].file = temp.file;
- inst->src[i].reg = temp.reg;
+ inst->src[i].nr = temp.nr;
inst->src[i].reg_offset = temp.reg_offset;
inst->src[i].reladdr = NULL;
}
* on, don't do dependency control across the read.
*/
for (int i = 0; i < 3; i++) {
- int reg = inst->src[i].reg + inst->src[i].reg_offset;
- if (inst->src[i].file == GRF) {
+ int reg = inst->src[i].nr + inst->src[i].reg_offset;
+ if (inst->src[i].file == VGRF) {
last_grf_write[reg] = NULL;
- } else if (inst->src[i].file == HW_REG) {
+ } else if (inst->src[i].file == FIXED_GRF) {
memset(last_grf_write, 0, sizeof(last_grf_write));
break;
}
/* Now, see if we can do dependency control for this instruction
* against a previous one writing to its destination.
*/
- int reg = inst->dst.reg + inst->dst.reg_offset;
- if (inst->dst.file == GRF) {
+ int reg = inst->dst.nr + inst->dst.reg_offset;
+ if (inst->dst.file == VGRF || inst->dst.file == FIXED_GRF) {
if (last_grf_write[reg] &&
!(inst->dst.writemask & grf_channels_written[reg])) {
last_grf_write[reg]->no_dd_clear = true;
last_mrf_write[reg] = inst;
mrf_channels_written[reg] |= inst->dst.writemask;
- } else if (inst->dst.reg == HW_REG) {
- if (inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE)
- memset(last_grf_write, 0, sizeof(last_grf_write));
- if (inst->dst.fixed_hw_reg.file == BRW_MESSAGE_REGISTER_FILE)
- memset(last_mrf_write, 0, sizeof(last_mrf_write));
}
}
}
int swizzle_mask)
{
/* Gen6 MATH instructions can not execute in align16 mode, so swizzles
- * or writemasking are not allowed.
+ * are not allowed.
*/
- if (devinfo->gen == 6 && is_math() &&
- (swizzle != BRW_SWIZZLE_XYZW || dst_writemask != WRITEMASK_XYZW))
+ if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
+ return false;
+
+ if (!can_do_writemask(devinfo) && dst_writemask != WRITEMASK_XYZW)
return false;
/* If this instruction sets anything not referenced by swizzle, then we'd
if (mlen > 0)
return false;
- /* We can't use swizzles on the accumulator and that's really the only
- * HW_REG we would care to reswizzle so just disallow them all.
- */
for (int i = 0; i < 3; i++) {
- if (src[i].file == HW_REG)
+ if (src[i].is_accumulator())
return false;
}
next_ip++;
if (inst->opcode != BRW_OPCODE_MOV ||
- (inst->dst.file != GRF && inst->dst.file != MRF) ||
+ (inst->dst.file != VGRF && inst->dst.file != MRF) ||
inst->predicate ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate || inst->src[0].reladdr)
continue;
/* Remove no-op MOVs */
if (inst->dst.file == inst->src[0].file &&
- inst->dst.reg == inst->src[0].reg &&
+ inst->dst.nr == inst->src[0].nr &&
inst->dst.reg_offset == inst->src[0].reg_offset) {
bool is_nop_mov = true;
if (is_nop_mov) {
inst->remove(block);
+ progress = true;
continue;
}
}
if (devinfo->gen == 6) {
/* gen6 math instructions must have the destination be
- * GRF, so no compute-to-MRF for them.
+ * VGRF, so no compute-to-MRF for them.
*/
if (scan_inst->is_math()) {
break;
* in the register instead.
*/
if (to_mrf && scan_inst->mlen > 0) {
- if (inst->dst.reg >= scan_inst->base_mrf &&
- inst->dst.reg < scan_inst->base_mrf + scan_inst->mlen) {
+ if (inst->dst.nr >= scan_inst->base_mrf &&
+ inst->dst.nr < scan_inst->base_mrf + scan_inst->mlen) {
break;
}
} else {
*/
vec4_instruction *scan_inst = _scan_inst;
while (scan_inst != inst) {
- if (scan_inst->dst.file == GRF &&
- scan_inst->dst.reg == inst->src[0].reg &&
+ if (scan_inst->dst.file == VGRF &&
+ scan_inst->dst.nr == inst->src[0].nr &&
scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
scan_inst->reswizzle(inst->dst.writemask,
inst->src[0].swizzle);
scan_inst->dst.file = inst->dst.file;
- scan_inst->dst.reg = inst->dst.reg;
+ scan_inst->dst.nr = inst->dst.nr;
scan_inst->dst.reg_offset = inst->dst.reg_offset;
if (inst->saturate &&
inst->dst.type != scan_inst->dst.type) {
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
if (depth == 0) {
inst->opcode = BRW_OPCODE_MOV;
- inst->src[0] = src_reg(0);
+ inst->src[0] = brw_imm_d(0);
inst->force_writemask_all = true;
progress = true;
}
* to split.
*/
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF && inst->regs_written > 1)
- split_grf[inst->dst.reg] = false;
+ if (inst->dst.file == VGRF && inst->regs_written > 1)
+ split_grf[inst->dst.nr] = false;
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF && inst->regs_read(i) > 1)
- split_grf[inst->src[i].reg] = false;
+ if (inst->src[i].file == VGRF && inst->regs_read(i) > 1)
+ split_grf[inst->src[i].nr] = false;
}
}
}
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF && split_grf[inst->dst.reg] &&
+ if (inst->dst.file == VGRF && split_grf[inst->dst.nr] &&
inst->dst.reg_offset != 0) {
- inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
+ inst->dst.nr = (new_virtual_grf[inst->dst.nr] +
inst->dst.reg_offset - 1);
inst->dst.reg_offset = 0;
}
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF && split_grf[inst->src[i].reg] &&
+ if (inst->src[i].file == VGRF && split_grf[inst->src[i].nr] &&
inst->src[i].reg_offset != 0) {
- inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
+ inst->src[i].nr = (new_virtual_grf[inst->src[i].nr] +
inst->src[i].reg_offset - 1);
inst->src[i].reg_offset = 0;
}
pred_ctrl_align16[inst->predicate]);
}
- fprintf(file, "%s", brw_instruction_name(inst->opcode));
+ fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
if (inst->saturate)
fprintf(file, ".sat");
if (inst->conditional_mod) {
fprintf(file, " ");
switch (inst->dst.file) {
- case GRF:
- fprintf(file, "vgrf%d.%d", inst->dst.reg, inst->dst.reg_offset);
+ case VGRF:
+ fprintf(file, "vgrf%d.%d", inst->dst.nr, inst->dst.reg_offset);
+ break;
+ case FIXED_GRF:
+ fprintf(file, "g%d", inst->dst.nr);
break;
case MRF:
- fprintf(file, "m%d", inst->dst.reg);
+ fprintf(file, "m%d", inst->dst.nr);
break;
- case HW_REG:
- if (inst->dst.fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->dst.fixed_hw_reg.nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->dst.fixed_hw_reg.subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->dst.fixed_hw_reg.subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->dst.fixed_hw_reg.nr & 0xf,
- inst->dst.fixed_hw_reg.subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->dst.fixed_hw_reg.nr & 0xf,
- inst->dst.fixed_hw_reg.subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->dst.fixed_hw_reg.nr);
+ case ARF:
+ switch (inst->dst.nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
}
- if (inst->dst.fixed_hw_reg.subnr)
- fprintf(file, "+%d", inst->dst.fixed_hw_reg.subnr);
+ if (inst->dst.subnr)
+ fprintf(file, "+%d", inst->dst.subnr);
break;
case BAD_FILE:
fprintf(file, "(null)");
break;
- default:
- fprintf(file, "???");
- break;
+ case IMM:
+ case ATTR:
+ case UNIFORM:
+ unreachable("not reached");
}
if (inst->dst.writemask != WRITEMASK_XYZW) {
fprintf(file, ".");
if (inst->src[i].abs)
fprintf(file, "|");
switch (inst->src[i].file) {
- case GRF:
- fprintf(file, "vgrf%d", inst->src[i].reg);
+ case VGRF:
+ fprintf(file, "vgrf%d", inst->src[i].nr);
+ break;
+ case FIXED_GRF:
+ fprintf(file, "g%d", inst->src[i].nr);
break;
case ATTR:
- fprintf(file, "attr%d", inst->src[i].reg);
+ fprintf(file, "attr%d", inst->src[i].nr);
break;
case UNIFORM:
- fprintf(file, "u%d", inst->src[i].reg);
+ fprintf(file, "u%d", inst->src[i].nr);
break;
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
- fprintf(file, "%fF", inst->src[i].fixed_hw_reg.dw1.f);
+ fprintf(file, "%fF", inst->src[i].f);
break;
case BRW_REGISTER_TYPE_D:
- fprintf(file, "%dD", inst->src[i].fixed_hw_reg.dw1.d);
+ fprintf(file, "%dD", inst->src[i].d);
break;
case BRW_REGISTER_TYPE_UD:
- fprintf(file, "%uU", inst->src[i].fixed_hw_reg.dw1.ud);
+ fprintf(file, "%uU", inst->src[i].ud);
break;
case BRW_REGISTER_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
- brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 0) & 0xff),
- brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 8) & 0xff),
- brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 16) & 0xff),
- brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 24) & 0xff));
+ brw_vf_to_float((inst->src[i].ud >> 0) & 0xff),
+ brw_vf_to_float((inst->src[i].ud >> 8) & 0xff),
+ brw_vf_to_float((inst->src[i].ud >> 16) & 0xff),
+ brw_vf_to_float((inst->src[i].ud >> 24) & 0xff));
break;
default:
fprintf(file, "???");
break;
}
break;
- case HW_REG:
- if (inst->src[i].fixed_hw_reg.negate)
- fprintf(file, "-");
- if (inst->src[i].fixed_hw_reg.abs)
- fprintf(file, "|");
- if (inst->src[i].fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->src[i].fixed_hw_reg.nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->src[i].fixed_hw_reg.subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->src[i].fixed_hw_reg.subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->src[i].fixed_hw_reg.nr & 0xf,
- inst->src[i].fixed_hw_reg.subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->src[i].fixed_hw_reg.nr & 0xf,
- inst->src[i].fixed_hw_reg.subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->src[i].fixed_hw_reg.nr);
+ case ARF:
+ switch (inst->src[i].nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
}
- if (inst->src[i].fixed_hw_reg.subnr)
- fprintf(file, "+%d", inst->src[i].fixed_hw_reg.subnr);
- if (inst->src[i].fixed_hw_reg.abs)
- fprintf(file, "|");
+ if (inst->src[i].subnr)
+ fprintf(file, "+%d", inst->src[i].subnr);
break;
case BAD_FILE:
fprintf(file, "(null)");
break;
- default:
- fprintf(file, "???");
- break;
+ case MRF:
+ unreachable("not reached");
}
/* Don't print .0; and only VGRFs have reg_offsets and sizes */
if (inst->src[i].reg_offset != 0 &&
- inst->src[i].file == GRF &&
- alloc.sizes[inst->src[i].reg] != 1)
+ inst->src[i].file == VGRF &&
+ alloc.sizes[inst->src[i].nr] != 1)
fprintf(file, ".%d", inst->src[i].reg_offset);
if (inst->src[i].file != IMM) {
fprintf(file, ", ");
}
+ if (inst->force_writemask_all)
+ fprintf(file, " NoMask");
+
fprintf(file, "\n");
}
bool interleaved)
{
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- /* We have to support ATTR as a destination for GL_FIXED fixup. */
- if (inst->dst.file == ATTR) {
- int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
-
- /* All attributes used in the shader need to have been assigned a
- * hardware register by the caller
- */
- assert(grf != 0);
-
- struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
- reg.type = inst->dst.type;
- reg.dw1.bits.writemask = inst->dst.writemask;
-
- inst->dst.file = HW_REG;
- inst->dst.fixed_hw_reg = reg;
- }
-
for (int i = 0; i < 3; i++) {
if (inst->src[i].file != ATTR)
continue;
- int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
+ int grf = attribute_map[inst->src[i].nr + inst->src[i].reg_offset];
/* All attributes used in the shader need to have been assigned a
* hardware register by the caller
assert(grf != 0);
struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
- reg.dw1.bits.swizzle = inst->src[i].swizzle;
+ reg.swizzle = inst->src[i].swizzle;
reg.type = inst->src[i].type;
if (inst->src[i].abs)
reg = brw_abs(reg);
if (inst->src[i].negate)
reg = negate(reg);
- inst->src[i].file = HW_REG;
- inst->src[i].fixed_hw_reg = reg;
+ inst->src[i] = reg;
}
}
}
vec4_vs_visitor::setup_attributes(int payload_reg)
{
int nr_attributes;
- int attribute_map[VERT_ATTRIB_MAX + 1];
+ int attribute_map[VERT_ATTRIB_MAX + 2];
memset(attribute_map, 0, sizeof(attribute_map));
nr_attributes = 0;
* don't represent it with a flag in inputs_read, so we call it
* VERT_ATTRIB_MAX.
*/
- if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid) {
+ if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid ||
+ vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) {
attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
+ nr_attributes++;
+ }
+
+ if (vs_prog_data->uses_drawid) {
+ attribute_map[VERT_ATTRIB_MAX + 1] = payload_reg + nr_attributes;
+ nr_attributes++;
}
lower_attributes_to_hw_regs(attribute_map, false /* interleaved */);
* matter what, or the GPU would hang.
*/
if (devinfo->gen < 6 && this->uniforms == 0) {
- assert(this->uniforms < this->uniform_array_size);
-
stage_prog_data->param =
reralloc(NULL, stage_prog_data->param, const gl_constant_value *, 4);
for (unsigned int i = 0; i < 4; i++) {
this->first_non_payload_grf = reg;
}
+bool
+vec4_visitor::lower_minmax()
+{
+ assert(devinfo->gen < 6);
+
+ bool progress = false;
+
+ foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
+ const vec4_builder ibld(this, block, inst);
+
+ if (inst->opcode == BRW_OPCODE_SEL &&
+ inst->predicate == BRW_PREDICATE_NONE) {
+ /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
+ * the original SEL.L/GE instruction
+ */
+ ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1],
+ inst->conditional_mod);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst->conditional_mod = BRW_CONDITIONAL_NONE;
+
+ progress = true;
+ }
+ }
+
+ if (progress)
+ invalidate_live_intervals();
+
+ return progress;
+}
+
src_reg
vec4_visitor::get_timestamp()
{
*/
src_reg reset_end = shader_end_time;
reset_end.swizzle = BRW_SWIZZLE_ZZZZ;
- vec4_instruction *test = emit(AND(dst_null_d(), reset_end, src_reg(1u)));
+ vec4_instruction *test = emit(AND(dst_null_ud(), reset_end, brw_imm_ud(1u)));
test->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
* is 2 cycles. Remove that overhead, so I can forget about that when
* trying to determine the time taken for single instructions.
*/
- emit(ADD(diff, src_reg(diff), src_reg(-2u)));
+ emit(ADD(diff, src_reg(diff), brw_imm_ud(-2u)));
emit_shader_time_write(0, src_reg(diff));
- emit_shader_time_write(1, src_reg(1u));
+ emit_shader_time_write(1, brw_imm_ud(1u));
emit(BRW_OPCODE_ELSE);
- emit_shader_time_write(2, src_reg(1u));
+ emit_shader_time_write(2, brw_imm_ud(1u));
emit(BRW_OPCODE_ENDIF);
}
offset.type = BRW_REGISTER_TYPE_UD;
int index = shader_time_index * 3 + shader_time_subindex;
- emit(MOV(offset, src_reg(index * SHADER_TIME_STRIDE)));
+ emit(MOV(offset, brw_imm_d(index * SHADER_TIME_STRIDE)));
time.type = BRW_REGISTER_TYPE_UD;
emit(MOV(time, value));
struct src_reg &src = inst->src[i];
struct brw_reg reg;
switch (src.file) {
- case GRF:
- reg = brw_vec8_grf(src.reg + src.reg_offset, 0);
+ case VGRF:
+ reg = brw_vec8_grf(src.nr + src.reg_offset, 0);
reg.type = src.type;
- reg.dw1.bits.swizzle = src.swizzle;
+ reg.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
break;
- case IMM:
- reg = brw_imm_reg(src.type);
- reg.dw1.ud = src.fixed_hw_reg.dw1.ud;
- break;
-
case UNIFORM:
reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
- (src.reg + src.reg_offset) / 2,
- ((src.reg + src.reg_offset) % 2) * 4),
+ (src.nr + src.reg_offset) / 2,
+ ((src.nr + src.reg_offset) % 2) * 4),
0, 4, 1);
reg.type = src.type;
- reg.dw1.bits.swizzle = src.swizzle;
+ reg.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
assert(!src.reladdr);
break;
- case HW_REG:
- assert(src.type == src.fixed_hw_reg.type);
+ case ARF:
+ case FIXED_GRF:
+ case IMM:
continue;
case BAD_FILE:
reg = brw_null_reg();
break;
- default:
+ case MRF:
+ case ATTR:
unreachable("not reached");
}
- src.fixed_hw_reg = reg;
+
+ src = reg;
+ }
+
+ if (inst->is_3src(devinfo)) {
+ /* 3-src instructions with scalar sources support arbitrary subnr,
+ * but don't actually use swizzles. Convert swizzle into subnr.
+ */
+ for (int i = 0; i < 3; i++) {
+ if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0) {
+ assert(brw_is_single_value_swizzle(inst->src[i].swizzle));
+ inst->src[i].subnr += 4 * BRW_GET_SWZ(inst->src[i].swizzle, 0);
+ }
+ }
}
dst_reg &dst = inst->dst;
struct brw_reg reg;
switch (inst->dst.file) {
- case GRF:
- reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
+ case VGRF:
+ reg = brw_vec8_grf(dst.nr + dst.reg_offset, 0);
reg.type = dst.type;
- reg.dw1.bits.writemask = dst.writemask;
+ reg.writemask = dst.writemask;
break;
case MRF:
- assert(((dst.reg + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen));
- reg = brw_message_reg(dst.reg + dst.reg_offset);
+ assert(((dst.nr + dst.reg_offset) & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
+ reg = brw_message_reg(dst.nr + dst.reg_offset);
reg.type = dst.type;
- reg.dw1.bits.writemask = dst.writemask;
+ reg.writemask = dst.writemask;
break;
- case HW_REG:
- assert(dst.type == dst.fixed_hw_reg.type);
- reg = dst.fixed_hw_reg;
+ case ARF:
+ case FIXED_GRF:
+ reg = dst.as_brw_reg();
break;
case BAD_FILE:
reg = brw_null_reg();
break;
- default:
+ case IMM:
+ case ATTR:
+ case UNIFORM:
unreachable("not reached");
}
- dst.fixed_hw_reg = reg;
+ dst = reg;
}
}
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) {
char filename[64];
- snprintf(filename, 64, "%s-%s-00-start",
+ snprintf(filename, 64, "%s-%s-00-00-start",
stage_abbrev, nir->info.name);
backend_shader::dump_instructions(filename);
OPT(dead_code_eliminate);
}
+ if (devinfo->gen <= 5 && OPT(lower_minmax)) {
+ OPT(opt_cmod_propagation);
+ OPT(opt_cse);
+ OPT(opt_copy_propagation);
+ OPT(dead_code_eliminate);
+ }
+
if (failed)
return false;
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
- const nir_shader *shader,
+ const nir_shader *src_shader,
gl_clip_plane *clip_planes,
bool use_legacy_snorm_formula,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str)
{
+ const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
+ nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
+ shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
+ is_scalar);
+ brw_nir_lower_vs_inputs(shader, compiler->devinfo, is_scalar,
+ use_legacy_snorm_formula, key->gl_attrib_wa_flags);
+ brw_nir_lower_vue_outputs(shader, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
+
const unsigned *assembly = NULL;
unsigned nr_attributes = _mesa_bitcount_64(prog_data->inputs_read);
* incoming vertex attribute. So, add an extra slot.
*/
if (shader->info.system_values_read &
- (BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
+ (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
+ BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
+ BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
nr_attributes++;
}
+ /* gl_DrawID has its very own vec4 */
+ if (shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) {
+ nr_attributes++;
+ }
+
+ unsigned nr_attribute_slots =
+ nr_attributes +
+ _mesa_bitcount_64(shader->info.double_inputs_read);
+
/* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
* Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
* vec4 mode, the hardware appears to wedge unless we read something.
*/
- if (compiler->scalar_vs)
- prog_data->base.urb_read_length = DIV_ROUND_UP(nr_attributes, 2);
+ if (is_scalar)
+ prog_data->base.urb_read_length =
+ DIV_ROUND_UP(nr_attribute_slots, 2);
else
- prog_data->base.urb_read_length = DIV_ROUND_UP(MAX2(nr_attributes, 1), 2);
+ prog_data->base.urb_read_length =
+ DIV_ROUND_UP(MAX2(nr_attribute_slots, 1), 2);
prog_data->nr_attributes = nr_attributes;
+ prog_data->nr_attribute_slots = nr_attribute_slots;
/* Since vertex shaders reuse the same VUE entry for inputs and outputs
* (overwriting the original contents), we need to make sure the size is
* the larger of the two.
*/
const unsigned vue_entries =
- MAX2(nr_attributes, (unsigned)prog_data->base.vue_map.num_slots);
+ MAX2(nr_attribute_slots, (unsigned)prog_data->base.vue_map.num_slots);
if (compiler->devinfo->gen == 6)
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8);
else
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);
- if (compiler->scalar_vs) {
+ if (is_scalar) {
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_visitor v(compiler, log_data, mem_ctx, key, &prog_data->base.base,
return NULL;
}
+ prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
+
fs_generator g(compiler, log_data, mem_ctx, (void *) key,
&prog_data->base.base, v.promoted_constants,
- v.runtime_check_aads_emit, "VS");
+ v.runtime_check_aads_emit, MESA_SHADER_VERTEX);
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
return NULL;
}
- vec4_generator g(compiler, log_data, &prog_data->base,
- mem_ctx, INTEL_DEBUG & DEBUG_VS, "vertex", "VS");
- assembly = g.generate_assembly(v.cfg, final_assembly_size, shader);
+ assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
+ shader, &prog_data->base, v.cfg,
+ final_assembly_size);
}
return assembly;
projects / mesa.git / blobdiff