i965/vs: Move class functions to brw_vec4.cpp.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 5238ff53c49e35fd924efdd3c85170bc37c4720a..37bb33531e28fc9affe82a6090d95addf26da3ee 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -31,6 +31,79 @@ extern "C" {
 
 namespace brw {
 
+/**
+ * Common helper for constructing swizzles.  When only a subset of
+ * channels of a vec4 are used, we don't want to reference the other
+ * channels, as that will tell optimization passes that those other
+ * channels are used.
+ */
+unsigned
+swizzle_for_size(int size)
+{
+   static const unsigned size_swizzles[4] = {
+      BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
+      BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
+      BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
+      BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
+   };
+
+   assert((size >= 1) && (size <= 4));
+   return size_swizzles[size - 1];
+}
+
+void
+src_reg::init()
+{
+   memset(this, 0, sizeof(*this));
+
+   this->file = BAD_FILE;
+}
+
+src_reg::src_reg(register_file file, int reg, const glsl_type *type)
+{
+   init();
+
+   this->file = file;
+   this->reg = reg;
+   if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
+      this->swizzle = swizzle_for_size(type->vector_elements);
+   else
+      this->swizzle = SWIZZLE_XYZW;
+}
+
+/** Generic unset register constructor. */
+src_reg::src_reg()
+{
+   init();
+}
+
+src_reg::src_reg(float f)
+{
+   init();
+
+   this->file = IMM;
+   this->type = BRW_REGISTER_TYPE_F;
+   this->imm.f = f;
+}
+
+src_reg::src_reg(uint32_t u)
+{
+   init();
+
+   this->file = IMM;
+   this->type = BRW_REGISTER_TYPE_UD;
+   this->imm.u = u;
+}
+
+src_reg::src_reg(int32_t i)
+{
+   init();
+
+   this->file = IMM;
+   this->type = BRW_REGISTER_TYPE_D;
+   this->imm.i = i;
+}
+
 bool
 vec4_instruction::is_tex()
 {
@@ -41,6 +114,46 @@ vec4_instruction::is_tex()
           opcode == SHADER_OPCODE_TXS);
 }
 
+void
+dst_reg::init()
+{
+   memset(this, 0, sizeof(*this));
+   this->file = BAD_FILE;
+   this->writemask = WRITEMASK_XYZW;
+}
+
+dst_reg::dst_reg()
+{
+   init();
+}
+
+dst_reg::dst_reg(register_file file, int reg)
+{
+   init();
+
+   this->file = file;
+   this->reg = reg;
+}
+
+dst_reg::dst_reg(register_file file, int reg, const glsl_type *type,
+                 int writemask)
+{
+   init();
+
+   this->file = file;
+   this->reg = reg;
+   this->type = brw_type_for_base_type(type);
+   this->writemask = writemask;
+}
+
+dst_reg::dst_reg(struct brw_reg reg)
+{
+   init();
+
+   this->file = HW_REG;
+   this->fixed_hw_reg = reg;
+}
+
 bool
 vec4_instruction::is_math()
 {