intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c97839641e1bf2eb33c24572f9d93c3500698a90..ab472b009ec9856159b318509fa256456a9c7354 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -260,6 +260,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case VS_OPCODE_SCRATCH_WRITE:
       return 3;
    case GS_OPCODE_URB_WRITE:
+   case GS_OPCODE_THREAD_END:
       return 0;
    case SHADER_OPCODE_SHADER_TIME_ADD:
       return 0;
@@ -1270,6 +1271,7 @@ vec4_visitor::setup_uniforms(int reg)
    if (brw->gen < 6 && this->uniforms == 0) {
       this->uniform_vector_size[this->uniforms] = 1;
 
+      prog_data->param = reralloc(NULL, prog_data->param, const float *, 4);
       for (unsigned int i = 0; i < 4; i++) {
         unsigned int slot = this->uniforms * 4 + i;
         static float zero = 0.0;