this->fixed_hw_reg.dw1.d = i;
}
+src_reg::src_reg(uint8_t vf[4])
+{
+ init();
+
+ this->file = IMM;
+ this->type = BRW_REGISTER_TYPE_VF;
+ memcpy(&this->fixed_hw_reg.dw1.ud, vf, sizeof(unsigned));
+}
+
src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
{
init();
this->fixed_hw_reg = reg.fixed_hw_reg;
}
+bool
+dst_reg::equals(const dst_reg &r) const
+{
+ return (file == r.file &&
+ reg == r.reg &&
+ reg_offset == r.reg_offset &&
+ type == r.type &&
+ negate == r.negate &&
+ abs == r.abs &&
+ writemask == r.writemask &&
+ (reladdr == r.reladdr ||
+ (reladdr && r.reladdr && reladdr->equals(*r.reladdr))) &&
+ memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
+ sizeof(fixed_hw_reg)) == 0);
+}
+
bool
vec4_instruction::is_send_from_grf()
{
}
}
+unsigned
+vec4_instruction::regs_read(unsigned arg) const
+{
+ if (src[arg].file == BAD_FILE)
+ return 0;
+
+ switch (opcode) {
+ case SHADER_OPCODE_SHADER_TIME_ADD:
+ return arg == 0 ? mlen : 1;
+
+ case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
+ return arg == 1 ? mlen : 1;
+
+ default:
+ return 1;
+ }
+}
+
bool
vec4_instruction::can_do_source_mods(struct brw_context *brw)
{
int
vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
{
- if (inst->mlen == 0)
+ if (inst->mlen == 0 || inst->is_send_from_grf())
return 0;
switch (inst->opcode) {
sizeof(fixed_hw_reg)) == 0);
}
+bool
+vec4_visitor::opt_vector_float()
+{
+ bool progress = false;
+
+ int last_reg = -1, last_reg_offset = -1;
+ enum register_file last_reg_file = BAD_FILE;
+
+ int remaining_channels = 0;
+ uint8_t imm[4];
+ int inst_count = 0;
+ vec4_instruction *imm_inst[4];
+
+ foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
+ if (last_reg != inst->dst.reg ||
+ last_reg_offset != inst->dst.reg_offset ||
+ last_reg_file != inst->dst.file) {
+ last_reg = inst->dst.reg;
+ last_reg_offset = inst->dst.reg_offset;
+ last_reg_file = inst->dst.file;
+ remaining_channels = WRITEMASK_XYZW;
+
+ inst_count = 0;
+ }
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->dst.writemask == WRITEMASK_XYZW ||
+ inst->src[0].file != IMM)
+ continue;
+
+ int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.dw1.f);
+ if (vf == -1)
+ continue;
+
+ if ((inst->dst.writemask & WRITEMASK_X) != 0)
+ imm[0] = vf;
+ if ((inst->dst.writemask & WRITEMASK_Y) != 0)
+ imm[1] = vf;
+ if ((inst->dst.writemask & WRITEMASK_Z) != 0)
+ imm[2] = vf;
+ if ((inst->dst.writemask & WRITEMASK_W) != 0)
+ imm[3] = vf;
+
+ imm_inst[inst_count++] = inst;
+
+ remaining_channels &= ~inst->dst.writemask;
+ if (remaining_channels == 0) {
+ vec4_instruction *mov = MOV(inst->dst, imm);
+ mov->dst.type = BRW_REGISTER_TYPE_F;
+ mov->dst.writemask = WRITEMASK_XYZW;
+ inst->insert_after(block, mov);
+ last_reg = -1;
+
+ for (int i = 0; i < inst_count; i++) {
+ imm_inst[i]->remove(block);
+ }
+ progress = true;
+ }
+ }
+
+ if (progress)
+ invalidate_live_intervals();
+
+ return progress;
+}
+
/* Replaces unused channels of a swizzle with channels that are used.
*
* For instance, this pass transforms
bool progress = false;
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG)
+ if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG ||
+ inst->is_send_from_grf())
continue;
int swizzle[4];
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
switch (inst->opcode) {
+ case BRW_OPCODE_MOV:
+ if (inst->src[0].file != IMM)
+ break;
+
+ if (inst->saturate) {
+ if (inst->dst.type != inst->src[0].type)
+ assert(!"unimplemented: saturate mixed types");
+
+ if (brw_saturate_immediate(inst->dst.type,
+ &inst->src[0].fixed_hw_reg)) {
+ inst->saturate = false;
+ progress = true;
+ }
+ }
+ break;
+
case VEC4_OPCODE_UNPACK_UNIFORM:
if (inst->src[0].file != UNIFORM) {
inst->opcode = BRW_OPCODE_MOV;
inst->opcode = BRW_OPCODE_MOV;
inst->src[1] = src_reg();
progress = true;
+ } else if (inst->src[1].is_negative_one()) {
+ inst->opcode = BRW_OPCODE_MOV;
+ inst->src[0].negate = !inst->src[0].negate;
+ inst->src[1] = src_reg();
+ progress = true;
}
break;
+ case BRW_OPCODE_CMP:
+ if (inst->conditional_mod == BRW_CONDITIONAL_GE &&
+ inst->src[0].abs &&
+ inst->src[0].negate &&
+ inst->src[1].is_zero()) {
+ inst->src[0].abs = false;
+ inst->src[0].negate = false;
+ inst->conditional_mod = BRW_CONDITIONAL_Z;
+ progress = true;
+ break;
+ }
+ break;
case SHADER_OPCODE_RCP: {
vec4_instruction *prev = (vec4_instruction *)inst->prev;
if (prev->opcode == SHADER_OPCODE_SQRT) {
(reg.type == BRW_REGISTER_TYPE_UD || \
reg.type == BRW_REGISTER_TYPE_D)
- /* From the destination hazard section of the spec:
- * > Instructions other than send, may use this control as long as operations
- * > that have different pipeline latencies are not mixed.
+ /* "When source or destination datatype is 64b or operation is integer DWord
+ * multiply, DepCtrl must not be used."
+ * May apply to future SoCs as well.
*/
- if (brw->gen >= 8) {
+ if (brw->is_cherryview) {
if (inst->opcode == BRW_OPCODE_MUL &&
IS_DWORD(inst->src[0]) &&
IS_DWORD(inst->src[1]))
}
#undef IS_DWORD
+ if (brw->gen >= 8) {
+ if (inst->opcode == BRW_OPCODE_F32TO16)
+ return true;
+ }
+
/*
* mlen:
* In the presence of send messages, totally interrupt dependency
void
vec4_visitor::split_virtual_grfs()
{
- int num_vars = this->virtual_grf_count;
+ int num_vars = this->alloc.count;
int new_virtual_grf[num_vars];
bool split_grf[num_vars];
/* Try to split anything > 0 sized. */
for (int i = 0; i < num_vars; i++) {
- split_grf[i] = this->virtual_grf_sizes[i] != 1;
+ split_grf[i] = this->alloc.sizes[i] != 1;
}
/* Check that the instructions are compatible with the registers we're trying
if (!split_grf[i])
continue;
- new_virtual_grf[i] = virtual_grf_alloc(1);
- for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
- int reg = virtual_grf_alloc(1);
+ new_virtual_grf[i] = alloc.allocate(1);
+ for (unsigned j = 2; j < this->alloc.sizes[i]; j++) {
+ unsigned reg = alloc.allocate(1);
assert(reg == new_virtual_grf[i] + j - 1);
(void) reg;
}
- this->virtual_grf_sizes[i] = 1;
+ this->alloc.sizes[i] = 1;
}
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
vec4_instruction *inst = (vec4_instruction *)be_inst;
if (inst->predicate) {
- fprintf(file, "(%cf0) ",
- inst->predicate_inverse ? '-' : '+');
+ fprintf(file, "(%cf0.%d) ",
+ inst->predicate_inverse ? '-' : '+',
+ inst->flag_subreg);
}
fprintf(file, "%s", brw_instruction_name(inst->opcode));
+ if (inst->saturate)
+ fprintf(file, ".sat");
if (inst->conditional_mod) {
fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
+ if (!inst->predicate &&
+ (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+ inst->opcode != BRW_OPCODE_IF &&
+ inst->opcode != BRW_OPCODE_WHILE))) {
+ fprintf(file, ".f0.%d", inst->flag_subreg);
+ }
}
fprintf(file, " ");
fprintf(file, "%uU", inst->src[i].fixed_hw_reg.dw1.ud);
break;
case BRW_REGISTER_TYPE_VF:
- fprintf(stderr, "[%-gF, %-gF, %-gF, %-gF]",
+ fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 16) & 0xff),
/* Don't print .0; and only VGRFs have reg_offsets and sizes */
if (inst->src[i].reg_offset != 0 &&
inst->src[i].file == GRF &&
- virtual_grf_sizes[inst->src[i].reg] != 1)
+ alloc.sizes[inst->src[i].reg] != 1)
fprintf(file, ".%d", inst->src[i].reg_offset);
if (inst->src[i].file != IMM) {
src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
0,
+ 0,
+ 0,
BRW_REGISTER_TYPE_UD,
BRW_VERTICAL_STRIDE_0,
BRW_WIDTH_4,
time.type = BRW_REGISTER_TYPE_UD;
emit(MOV(time, src_reg(value)));
- emit(SHADER_OPCODE_SHADER_TIME_ADD, dst_reg(), src_reg(dst));
+ vec4_instruction *inst =
+ emit(SHADER_OPCODE_SHADER_TIME_ADD, dst_reg(), src_reg(dst));
+ inst->mlen = 2;
}
bool
const char *stage_name = stage == MESA_SHADER_GEOMETRY ? "gs" : "vs";
-#define OPT(pass, args...) do { \
+#define OPT(pass, args...) ({ \
pass_num++; \
bool this_progress = pass(args); \
\
} \
\
progress = progress || this_progress; \
- } while (false)
+ this_progress; \
+ })
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) {
bool progress;
int iteration = 0;
+ int pass_num = 0;
do {
progress = false;
+ pass_num = 0;
iteration++;
- int pass_num = 0;
OPT(opt_reduce_swizzle);
OPT(dead_code_eliminate);
OPT(opt_register_coalesce);
} while (progress);
+ pass_num = 0;
+
+ if (OPT(opt_vector_float)) {
+ OPT(opt_cse);
+ OPT(opt_copy_propagation, false);
+ OPT(opt_copy_propagation, true);
+ OPT(dead_code_eliminate);
+ }
if (failed)
return false;
if (false) {
/* Debug of register spilling: Go spill everything. */
- const int grf_count = virtual_grf_count;
- float spill_costs[virtual_grf_count];
- bool no_spill[virtual_grf_count];
+ const int grf_count = alloc.count;
+ float spill_costs[alloc.count];
+ bool no_spill[alloc.count];
evaluate_spill_costs(spill_costs, no_spill);
for (int i = 0; i < grf_count; i++) {
if (no_spill[i])
}
fs_generator g(brw, mem_ctx, (void *) &c->key, &prog_data->base.base,
- &c->vp->program.Base, v.runtime_check_aads_emit);
+ &c->vp->program.Base, v.promoted_constants,
+ v.runtime_check_aads_emit, "VS");
if (INTEL_DEBUG & DEBUG_VS) {
char *name = ralloc_asprintf(mem_ctx, "%s vertex shader %d",
prog->Label ? prog->Label : "unnamed",
}
vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
- mem_ctx, INTEL_DEBUG & DEBUG_VS);
+ mem_ctx, INTEL_DEBUG & DEBUG_VS, "vertex", "VS");
assembly = g.generate_assembly(v.cfg, final_assembly_size);
}
struct brw_vue_prog_key *key,
GLuint id, struct gl_program *prog)
{
+ struct brw_context *brw = brw_context(ctx);
key->program_string_id = id;
+ const bool has_shader_channel_select = brw->is_haswell || brw->gen >= 8;
unsigned sampler_count = _mesa_fls(prog->SamplersUsed);
for (unsigned i = 0; i < sampler_count; i++) {
- if (prog->ShadowSamplers & (1 << i)) {
+ if (!has_shader_channel_select && (prog->ShadowSamplers & (1 << i))) {
/* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
key->tex.swizzles[i] =
MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
projects / mesa.git / blobdiff