#ifndef BRW_VEC4_H
#define BRW_VEC4_H
-#include <stdint.h>
#include "brw_shader.h"
-#include "main/compiler.h"
-#include "program/hash_table.h"
#include "brw_program.h"
#ifdef __cplusplus
#include "brw_ir_vec4.h"
-
-extern "C" {
-#endif
-
-#include "brw_context.h"
-#include "brw_eu.h"
-#include "intel_asm_annotation.h"
-
-#ifdef __cplusplus
-}; /* extern "C" */
#endif
-#include "glsl/ir.h"
-#include "glsl/nir/nir.h"
+#include "compiler/glsl/ir.h"
+#include "compiler/nir/nir.h"
#ifdef __cplusplus
* for the ir->location's used.
*/
dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
+ dst_reg output_generic_reg[MAX_VARYINGS_INCL_PATCH][4];
+ unsigned output_generic_num_components[MAX_VARYINGS_INCL_PATCH][4];
const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
- int *uniform_size;
- int uniform_array_size; /*< Size of the uniform_size array */
int uniforms;
src_reg shader_start_time;
EMIT3(MAD)
EMIT2(ADDC)
EMIT2(SUBB)
+ EMIT1(DIM)
+
#undef EMIT1
#undef EMIT2
#undef EMIT3
uint32_t constant_offset,
src_reg offset_value,
src_reg mcs,
- bool is_cube_array,
+ uint32_t surface, src_reg surface_reg,
uint32_t sampler, src_reg sampler_reg);
- uint32_t gather_channel(unsigned gather_component, uint32_t sampler);
src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
- src_reg sampler);
+ src_reg surface);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
- void swizzle_result(ir_texture_opcode op, dst_reg dest,
- src_reg orig_val, uint32_t sampler,
- const glsl_type *dest_type);
void emit_ndc_computation();
void emit_psiz_and_flags(dst_reg reg);
vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
+ void emit_generic_urb_slot(dst_reg reg, int varying, int component);
virtual void emit_urb_slot(dst_reg reg, int varying);
void emit_shader_time_begin();
void emit_shader_time_end();
void emit_shader_time_write(int shader_time_subindex, src_reg value);
- void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
- dst_reg dst, src_reg offset, src_reg src0,
- src_reg src1);
-
- void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
- src_reg offset);
-
src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
src_reg *reladdr, int reg_offset);
- src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
- src_reg *reladdr, int reg_offset);
void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
dst_reg dst,
src_reg orig_src,
void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
dst_reg dst,
src_reg orig_src,
- int base_offset);
+ int base_offset,
+ src_reg indirect);
void emit_pull_constant_load_reg(dst_reg dst,
src_reg surf_index,
src_reg offset,
void resolve_ud_negate(src_reg *reg);
+ bool lower_minmax();
+
src_reg get_timestamp();
void dump_instruction(backend_instruction *inst);
bool is_high_sampler(src_reg sampler);
+ bool optimize_predicate(nir_alu_instr *instr, enum brw_predicate *predicate);
+
virtual void emit_nir_code();
- virtual void nir_setup_inputs();
virtual void nir_setup_uniforms();
virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
virtual void nir_setup_system_values();
virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
- dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
- dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
- dst_reg get_nir_dest(nir_dest dest);
- src_reg get_nir_src(nir_src src, enum brw_reg_type type,
+ dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type);
+ dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type);
+ dst_reg get_nir_dest(const nir_dest &dest);
+ src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
unsigned num_components = 4);
- src_reg get_nir_src(nir_src src, nir_alu_type type,
+ src_reg get_nir_src(const nir_src &src, nir_alu_type type,
unsigned num_components = 4);
- src_reg get_nir_src(nir_src src,
+ src_reg get_nir_src(const nir_src &src,
unsigned num_components = 4);
+ src_reg get_indirect_offset(nir_intrinsic_instr *instr);
- virtual dst_reg *make_reg_for_system_value(int location,
- const glsl_type *type) = 0;
+ virtual dst_reg *make_reg_for_system_value(int location) = 0;
dst_reg *nir_locals;
dst_reg *nir_ssa_values;
- src_reg *nir_inputs;
dst_reg *nir_system_values;
protected:
unsigned last_scratch; /**< measured in 32-byte (register size) units */
};
-
-/**
- * The vertex shader code generator.
- *
- * Translates VS IR to actual i965 assembly code.
- */
-class vec4_generator
-{
-public:
- vec4_generator(const struct brw_compiler *compiler, void *log_data,
- struct brw_vue_prog_data *prog_data,
- void *mem_ctx,
- bool debug_flag,
- const char *stage_name,
- const char *stage_abbrev);
- ~vec4_generator();
-
- const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size,
- const nir_shader *nir);
-
-private:
- void generate_code(const cfg_t *cfg, const nir_shader *nir);
-
- void generate_math1_gen4(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src);
- void generate_math2_gen4(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
- void generate_math_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
-
- void generate_tex(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src,
- struct brw_reg sampler_index);
-
- void generate_vs_urb_write(vec4_instruction *inst);
- void generate_gs_urb_write(vec4_instruction *inst);
- void generate_gs_urb_write_allocate(vec4_instruction *inst);
- void generate_gs_thread_end(vec4_instruction *inst);
- void generate_gs_set_write_offset(struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
- void generate_gs_set_vertex_count(struct brw_reg dst,
- struct brw_reg src);
- void generate_gs_svb_write(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
- void generate_gs_svb_set_destination_index(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src);
- void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
- void generate_gs_prepare_channel_masks(struct brw_reg dst);
- void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
- void generate_gs_get_instance_id(struct brw_reg dst);
- void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1,
- struct brw_reg src2);
- void generate_gs_ff_sync(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1);
- void generate_gs_set_primitive_id(struct brw_reg dst);
- void generate_oword_dual_block_offsets(struct brw_reg m1,
- struct brw_reg index);
- void generate_scratch_write(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src,
- struct brw_reg index);
- void generate_scratch_read(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg index);
- void generate_pull_constant_load(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg index,
- struct brw_reg offset);
- void generate_pull_constant_load_gen7(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg surf_index,
- struct brw_reg offset);
- void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
- struct brw_reg dst);
-
- void generate_get_buffer_size(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src,
- struct brw_reg index);
-
- void generate_unpack_flags(struct brw_reg dst);
-
- const struct brw_compiler *compiler;
- void *log_data; /* Passed to compiler->*_log functions */
-
- const struct brw_device_info *devinfo;
-
- struct brw_codegen *p;
-
- struct brw_vue_prog_data *prog_data;
-
- void *mem_ctx;
- const char *stage_name;
- const char *stage_abbrev;
- const bool debug_flag;
-};
-
} /* namespace brw */
#endif /* __cplusplus */
projects / mesa.git / blobdiff