* for the ir->location's used.
*/
dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
+ dst_reg output_generic_reg[MAX_VARYINGS_INCL_PATCH][4];
+ unsigned output_generic_num_components[MAX_VARYINGS_INCL_PATCH][4];
const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
int uniforms;
EMIT3(MAD)
EMIT2(ADDC)
EMIT2(SUBB)
+ EMIT1(DIM)
+
#undef EMIT1
#undef EMIT2
#undef EMIT3
uint32_t constant_offset,
src_reg offset_value,
src_reg mcs,
- bool is_cube_array,
uint32_t surface, src_reg surface_reg,
uint32_t sampler, src_reg sampler_reg);
void emit_ndc_computation();
void emit_psiz_and_flags(dst_reg reg);
vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
+ void emit_generic_urb_slot(dst_reg reg, int varying, int component);
virtual void emit_urb_slot(dst_reg reg, int varying);
void emit_shader_time_begin();
virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
- dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
- dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
- dst_reg get_nir_dest(nir_dest dest);
- src_reg get_nir_src(nir_src src, enum brw_reg_type type,
+ dst_reg get_nir_dest(const nir_dest &dest, enum brw_reg_type type);
+ dst_reg get_nir_dest(const nir_dest &dest, nir_alu_type type);
+ dst_reg get_nir_dest(const nir_dest &dest);
+ src_reg get_nir_src(const nir_src &src, enum brw_reg_type type,
unsigned num_components = 4);
- src_reg get_nir_src(nir_src src, nir_alu_type type,
+ src_reg get_nir_src(const nir_src &src, nir_alu_type type,
unsigned num_components = 4);
- src_reg get_nir_src(nir_src src,
+ src_reg get_nir_src(const nir_src &src,
unsigned num_components = 4);
src_reg get_indirect_offset(nir_intrinsic_instr *instr);