* channels, as that will tell optimization passes that those other
* channels are used.
*/
-static int
+static unsigned
swizzle_for_size(int size)
{
- int size_swizzles[4] = {
+ static const unsigned size_swizzles[4] = {
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
int reg_offset;
/** Register type. BRW_REGISTER_TYPE_* */
int type;
- bool sechalf;
struct brw_reg fixed_hw_reg;
- int smear; /* -1, or a channel of the reg to smear to all channels. */
/** Value for file == BRW_IMMMEDIATE_FILE */
union {
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
- this->imm.f = u;
+ this->imm.u = u;
}
src_reg(int32_t i)
}
bool equals(src_reg *r);
+ bool is_zero() const;
+ bool is_one() const;
src_reg(class vec4_visitor *v, const struct glsl_type *type);
this->reg = reg;
}
+ dst_reg(register_file file, int reg, const glsl_type *type, int writemask)
+ {
+ init();
+
+ this->file = file;
+ this->reg = reg;
+ this->type = brw_type_for_base_type(type);
+ this->writemask = writemask;
+ }
+
dst_reg(struct brw_reg reg)
{
init();
int conditional_mod; /**< BRW_CONDITIONAL_* */
int sampler;
+ uint32_t texture_offset; /**< Texture Offset bitfield */
int target; /**< MRT target. */
bool shadow_compare;
ir_instruction *ir;
const char *annotation;
+ bool is_tex();
bool is_math();
};
int first_non_payload_grf;
int *virtual_grf_def;
int *virtual_grf_use;
+ dst_reg userplane[MAX_CLIP_PLANES];
/**
* This is the size to be used for an array with an element per
void fail(const char *msg, ...);
int virtual_grf_alloc(int size);
+ void setup_uniform_clipplane_values();
int setup_uniform_values(int loc, const glsl_type *type);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_attributes(int payload_reg);
bool dead_code_eliminate();
bool virtual_grf_interferes(int a, int b);
bool opt_copy_propagation();
+ bool opt_algebraic();
+ bool opt_compute_to_mrf();
vec4_instruction *emit(vec4_instruction *inst);
vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+ int implied_mrf_writes(vec4_instruction *inst);
+
bool try_rewrite_rhs_to_dst(ir_assignment *ir,
dst_reg dst,
src_reg src,
void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
+ void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
+
void emit_ndc_computation();
void emit_psiz_and_flags(struct brw_reg reg);
void emit_clip_distances(struct brw_reg reg, int offset);
+ void emit_generic_urb_slot(dst_reg reg, int vert_result);
void emit_urb_slot(int mrf, int vert_result);
void emit_urb_writes(void);
src_reg orig_src,
int base_offset);
- GLboolean try_emit_sat(ir_expression *ir);
+ bool try_emit_sat(ir_expression *ir);
+ void resolve_ud_negate(src_reg *reg);
bool process_move_condition(ir_rvalue *ir);
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
+ void generate_math2_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
+
+ void generate_tex(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src);
void generate_urb_write(vec4_instruction *inst);
void generate_oword_dual_block_offsets(struct brw_reg m1,