mesa: add/update comments in _mesa_copy_buffer_subdata()

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 8c613bd957240843d604c4689acd1f5ec4889096..2555fa71059d6645c61d9fe6532859715b80fd4f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -47,10 +47,10 @@ class dst_reg;
  * channels, as that will tell optimization passes that those other
  * channels are used.
  */
-static int
+static unsigned
 swizzle_for_size(int size)
 {
-   int size_swizzles[4] = {
+   static const unsigned size_swizzles[4] = {
       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
@@ -83,9 +83,7 @@ public:
    int reg_offset;
    /** Register type.  BRW_REGISTER_TYPE_* */
    int type;
-   bool sechalf;
    struct brw_reg fixed_hw_reg;
-   int smear; /* -1, or a channel of the reg to smear to all channels. */
 
    /** Value for file == BRW_IMMMEDIATE_FILE */
    union {
@@ -150,7 +148,7 @@ public:
 
       this->file = IMM;
       this->type = BRW_REGISTER_TYPE_UD;
-      this->imm.f = u;
+      this->imm.u = u;
    }
 
    src_reg(int32_t i)
@@ -162,6 +160,10 @@ public:
       this->imm.i = i;
    }
 
+   bool equals(src_reg *r);
+   bool is_zero() const;
+   bool is_one() const;
+
    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 
    explicit src_reg(dst_reg reg);
@@ -208,6 +210,16 @@ public:
       this->reg = reg;
    }
 
+   dst_reg(register_file file, int reg, const glsl_type *type, int writemask)
+   {
+      init();
+
+      this->file = file;
+      this->reg = reg;
+      this->type = brw_type_for_base_type(type);
+      this->writemask = writemask;
+   }
+
    dst_reg(struct brw_reg reg)
    {
       init();
@@ -259,6 +271,7 @@ public:
    int conditional_mod; /**< BRW_CONDITIONAL_* */
 
    int sampler;
+   uint32_t texture_offset; /**< Texture Offset bitfield */
    int target; /**< MRT target. */
    bool shadow_compare;
 
@@ -273,6 +286,9 @@ public:
     */
    ir_instruction *ir;
    const char *annotation;
+
+   bool is_tex();
+   bool is_math();
 };
 
 class vec4_visitor : public ir_visitor
@@ -320,6 +336,16 @@ public:
    int first_non_payload_grf;
    int *virtual_grf_def;
    int *virtual_grf_use;
+   dst_reg userplane[MAX_CLIP_PLANES];
+
+   /**
+    * This is the size to be used for an array with an element per
+    * reg_offset
+    */
+   int virtual_grf_reg_count;
+   /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
+   int *virtual_grf_reg_map;
+
    bool live_intervals_valid;
 
    dst_reg *variable_storage(ir_variable *var);
@@ -361,6 +387,7 @@ public:
     * for the ir->location's used.
     */
    dst_reg output_reg[BRW_VERT_RESULT_MAX];
+   const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
    int uniform_size[MAX_UNIFORMS];
    int uniform_vector_size[MAX_UNIFORMS];
    int uniforms;
@@ -371,6 +398,7 @@ public:
    void fail(const char *msg, ...);
 
    int virtual_grf_alloc(int size);
+   void setup_uniform_clipplane_values();
    int setup_uniform_values(int loc, const glsl_type *type);
    void setup_builtin_uniform_values(ir_variable *ir);
    int setup_attributes(int payload_reg);
@@ -380,11 +408,15 @@ public:
    void reg_allocate();
    void move_grf_array_access_to_scratch();
    void move_uniform_array_access_to_pull_constants();
+   void move_push_constants_to_pull_constants();
    void split_uniform_registers();
    void pack_uniform_registers();
    void calculate_live_intervals();
    bool dead_code_eliminate();
    bool virtual_grf_interferes(int a, int b);
+   bool opt_copy_propagation();
+   bool opt_algebraic();
+   bool opt_compute_to_mrf();
 
    vec4_instruction *emit(vec4_instruction *inst);
 
@@ -424,6 +456,8 @@ public:
    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 
+   int implied_mrf_writes(vec4_instruction *inst);
+
    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
                               dst_reg dst,
                               src_reg src,
@@ -433,12 +467,12 @@ public:
    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
    void visit_instructions(const exec_list *list);
 
-   void emit_bool_to_cond_code(ir_rvalue *ir);
+   void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
    void emit_if_gen6(ir_if *ir);
 
    void emit_block_move(dst_reg *dst, src_reg *src,
-                       const struct glsl_type *type, bool predicated);
+                       const struct glsl_type *type, uint32_t predicate);
 
    void emit_constant_values(dst_reg *dst, ir_constant *value);
 
@@ -463,10 +497,13 @@ public:
    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 
+   void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
+
    void emit_ndc_computation();
    void emit_psiz_and_flags(struct brw_reg reg);
-   int emit_vue_header_gen6(int header_mrf);
-   int emit_vue_header_gen4(int header_mrf);
+   void emit_clip_distances(struct brw_reg reg, int offset);
+   void emit_generic_urb_slot(dst_reg reg, int vert_result);
+   void emit_urb_slot(int mrf, int vert_result);
    void emit_urb_writes(void);
 
    src_reg get_scratch_offset(vec4_instruction *inst,
@@ -486,7 +523,8 @@ public:
                                src_reg orig_src,
                                int base_offset);
 
-   GLboolean try_emit_sat(ir_expression *ir);
+   bool try_emit_sat(ir_expression *ir);
+   void resolve_ud_negate(src_reg *reg);
 
    bool process_move_condition(ir_rvalue *ir);
 
@@ -509,6 +547,14 @@ public:
                            struct brw_reg dst,
                            struct brw_reg src0,
                            struct brw_reg src1);
+   void generate_math2_gen7(vec4_instruction *inst,
+                           struct brw_reg dst,
+                           struct brw_reg src0,
+                           struct brw_reg src1);
+
+   void generate_tex(vec4_instruction *inst,
+                    struct brw_reg dst,
+                    struct brw_reg src);
 
    void generate_urb_write(vec4_instruction *inst);
    void generate_oword_dual_block_offsets(struct brw_reg m1,