* channels, as that will tell optimization passes that those other
* channels are used.
*/
-static int
+static unsigned
swizzle_for_size(int size)
{
- int size_swizzles[4] = {
+ static const unsigned size_swizzles[4] = {
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
int reg_offset;
/** Register type. BRW_REGISTER_TYPE_* */
int type;
- bool sechalf;
struct brw_reg fixed_hw_reg;
- int smear; /* -1, or a channel of the reg to smear to all channels. */
/** Value for file == BRW_IMMMEDIATE_FILE */
union {
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
- this->imm.f = u;
+ this->imm.u = u;
}
src_reg(int32_t i)
this->imm.i = i;
}
+ bool equals(src_reg *r);
+ bool is_zero() const;
+ bool is_one() const;
+
src_reg(class vec4_visitor *v, const struct glsl_type *type);
explicit src_reg(dst_reg reg);
this->reg = reg;
}
+ dst_reg(register_file file, int reg, const glsl_type *type, int writemask)
+ {
+ init();
+
+ this->file = file;
+ this->reg = reg;
+ this->type = brw_type_for_base_type(type);
+ this->writemask = writemask;
+ }
+
dst_reg(struct brw_reg reg)
{
init();
int conditional_mod; /**< BRW_CONDITIONAL_* */
int sampler;
+ uint32_t texture_offset; /**< Texture Offset bitfield */
int target; /**< MRT target. */
bool shadow_compare;
*/
ir_instruction *ir;
const char *annotation;
+
+ bool is_tex();
+ bool is_math();
};
class vec4_visitor : public ir_visitor
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
}
- dst_reg dst_null_cmp()
- {
- if (intel->gen > 4)
- return dst_null_d();
- else
- return dst_null_f();
- }
-
struct brw_context *brw;
const struct gl_vertex_program *vp;
struct intel_context *intel;
int first_non_payload_grf;
int *virtual_grf_def;
int *virtual_grf_use;
+ dst_reg userplane[MAX_CLIP_PLANES];
+
+ /**
+ * This is the size to be used for an array with an element per
+ * reg_offset
+ */
+ int virtual_grf_reg_count;
+ /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
+ int *virtual_grf_reg_map;
+
bool live_intervals_valid;
dst_reg *variable_storage(ir_variable *var);
/* Regs for vertex results. Generated at ir_variable visiting time
* for the ir->location's used.
*/
- dst_reg output_reg[VERT_RESULT_MAX];
+ dst_reg output_reg[BRW_VERT_RESULT_MAX];
+ const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
int uniform_size[MAX_UNIFORMS];
int uniform_vector_size[MAX_UNIFORMS];
int uniforms;
void fail(const char *msg, ...);
int virtual_grf_alloc(int size);
+ void setup_uniform_clipplane_values();
int setup_uniform_values(int loc, const glsl_type *type);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_attributes(int payload_reg);
void reg_allocate();
void move_grf_array_access_to_scratch();
void move_uniform_array_access_to_pull_constants();
+ void move_push_constants_to_pull_constants();
void split_uniform_registers();
void pack_uniform_registers();
void calculate_live_intervals();
bool dead_code_eliminate();
bool virtual_grf_interferes(int a, int b);
+ bool opt_copy_propagation();
+ bool opt_algebraic();
+ bool opt_compute_to_mrf();
vec4_instruction *emit(vec4_instruction *inst);
vec4_instruction *emit(enum opcode opcode, dst_reg dst,
src_reg src0, src_reg src1, src_reg src2);
+ vec4_instruction *emit_before(vec4_instruction *inst,
+ vec4_instruction *new_inst);
+
vec4_instruction *MOV(dst_reg dst, src_reg src0);
vec4_instruction *NOT(dst_reg dst, src_reg src0);
vec4_instruction *RNDD(dst_reg dst, src_reg src0);
uint32_t condition);
vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
vec4_instruction *IF(uint32_t predicate);
+ vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
+ vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
+ vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+
+ int implied_mrf_writes(vec4_instruction *inst);
bool try_rewrite_rhs_to_dst(ir_assignment *ir,
dst_reg dst,
/** Walks an exec_list of ir_instruction and sends it through this visitor. */
void visit_instructions(const exec_list *list);
- void emit_bool_to_cond_code(ir_rvalue *ir);
+ void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
void emit_if_gen6(ir_if *ir);
void emit_block_move(dst_reg *dst, src_reg *src,
- const struct glsl_type *type, bool predicated);
+ const struct glsl_type *type, uint32_t predicate);
void emit_constant_values(dst_reg *dst, ir_constant *value);
void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
- int emit_vue_header_gen6(int header_mrf);
- int emit_vue_header_gen4(int header_mrf);
+ void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
+
+ void emit_ndc_computation();
+ void emit_psiz_and_flags(struct brw_reg reg);
+ void emit_clip_distances(struct brw_reg reg, int offset);
+ void emit_generic_urb_slot(dst_reg reg, int vert_result);
+ void emit_urb_slot(int mrf, int vert_result);
void emit_urb_writes(void);
src_reg get_scratch_offset(vec4_instruction *inst,
src_reg orig_src,
int base_offset);
- GLboolean try_emit_sat(ir_expression *ir);
+ bool try_emit_sat(ir_expression *ir);
+ void resolve_ud_negate(src_reg *reg);
bool process_move_condition(ir_rvalue *ir);
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
+ void generate_math2_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
+
+ void generate_tex(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src);
void generate_urb_write(vec4_instruction *inst);
void generate_oword_dual_block_offsets(struct brw_reg m1,
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