i965/vec4: Don't lose the force_writemask_all flag during CSE.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index e4d0cb75b02f796d1486b89b02de270647b8ba06..2fd2f29c4beb3533d1ae8744108799040a1b6c78 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -84,7 +84,6 @@ public:
                struct gl_shader_program *shader_prog,
                 gl_shader_stage stage,
                void *mem_ctx,
-                bool debug_flag,
                 bool no_spills,
                 shader_time_shader_type st_base,
                 shader_time_shader_type st_written,
@@ -257,7 +256,6 @@ public:
    vec4_instruction *IF(src_reg src0, src_reg src1,
                         enum brw_conditional_mod condition);
    vec4_instruction *IF(enum brw_predicate predicate);
-   EMIT1(PULL_CONSTANT_LOAD)
    EMIT1(SCRATCH_READ)
    EMIT2(SCRATCH_WRITE)
    EMIT3(LRP)
@@ -398,8 +396,6 @@ protected:
    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
    virtual int compute_array_stride(ir_dereference_array *ir);
 
-   const bool debug_flag;
-
 private:
    /**
     * If true, then register allocation should fail instead of spilling.