i965/vs: Remove dead fields of src_reg.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 77a28c7cda7e68336ef690397083f50ab9f3b7ec..317c981a40a3f5ab62e7ef05dc99a21d6139dd7a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -35,7 +35,7 @@ extern "C" {
 #include "brw_eu.h"
 };
 
-#include "../glsl/ir.h"
+#include "glsl/ir.h"
 
 namespace brw {
 
@@ -83,9 +83,7 @@ public:
    int reg_offset;
    /** Register type.  BRW_REGISTER_TYPE_* */
    int type;
-   bool sechalf;
    struct brw_reg fixed_hw_reg;
-   int smear; /* -1, or a channel of the reg to smear to all channels. */
 
    /** Value for file == BRW_IMMMEDIATE_FILE */
    union {
@@ -162,6 +160,10 @@ public:
       this->imm.i = i;
    }
 
+   bool equals(src_reg *r);
+   bool is_zero() const;
+   bool is_one() const;
+
    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 
    explicit src_reg(dst_reg reg);
@@ -239,6 +241,12 @@ public:
       return node;
    }
 
+   vec4_instruction(vec4_visitor *v, enum opcode opcode,
+                   dst_reg dst = dst_reg(),
+                   src_reg src0 = src_reg(),
+                   src_reg src1 = src_reg(),
+                   src_reg src2 = src_reg());
+
    struct brw_reg get_dst(void);
    struct brw_reg get_src(int i);
 
@@ -267,6 +275,8 @@ public:
     */
    ir_instruction *ir;
    const char *annotation;
+
+   bool is_math();
 };
 
 class vec4_visitor : public ir_visitor
@@ -286,14 +296,6 @@ public:
       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
    }
 
-   dst_reg dst_null_cmp()
-   {
-      if (intel->gen > 4)
-        return dst_null_d();
-      else
-        return dst_null_f();
-   }
-
    struct brw_context *brw;
    const struct gl_vertex_program *vp;
    struct intel_context *intel;
@@ -322,6 +324,15 @@ public:
    int first_non_payload_grf;
    int *virtual_grf_def;
    int *virtual_grf_use;
+
+   /**
+    * This is the size to be used for an array with an element per
+    * reg_offset
+    */
+   int virtual_grf_reg_count;
+   /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
+   int *virtual_grf_reg_map;
+
    bool live_intervals_valid;
 
    dst_reg *variable_storage(ir_variable *var);
@@ -362,8 +373,10 @@ public:
    /* Regs for vertex results.  Generated at ir_variable visiting time
     * for the ir->location's used.
     */
-   dst_reg output_reg[VERT_RESULT_MAX];
+   dst_reg output_reg[BRW_VERT_RESULT_MAX];
+   const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
    int uniform_size[MAX_UNIFORMS];
+   int uniform_vector_size[MAX_UNIFORMS];
    int uniforms;
 
    struct hash_table *variable_ht;
@@ -380,8 +393,17 @@ public:
    void reg_allocate_trivial();
    void reg_allocate();
    void move_grf_array_access_to_scratch();
+   void move_uniform_array_access_to_pull_constants();
+   void move_push_constants_to_pull_constants();
+   void split_uniform_registers();
+   void pack_uniform_registers();
    void calculate_live_intervals();
+   bool dead_code_eliminate();
    bool virtual_grf_interferes(int a, int b);
+   bool opt_copy_propagation();
+   bool opt_algebraic();
+
+   vec4_instruction *emit(vec4_instruction *inst);
 
    vec4_instruction *emit(enum opcode opcode);
 
@@ -393,6 +415,32 @@ public:
    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
                          src_reg src0, src_reg src1, src_reg src2);
 
+   vec4_instruction *emit_before(vec4_instruction *inst,
+                                vec4_instruction *new_inst);
+
+   vec4_instruction *MOV(dst_reg dst, src_reg src0);
+   vec4_instruction *NOT(dst_reg dst, src_reg src0);
+   vec4_instruction *RNDD(dst_reg dst, src_reg src0);
+   vec4_instruction *RNDE(dst_reg dst, src_reg src0);
+   vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
+   vec4_instruction *FRC(dst_reg dst, src_reg src0);
+   vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
+                        uint32_t condition);
+   vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
+   vec4_instruction *IF(uint32_t predicate);
+   vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
+   vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
+   vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+
    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
                               dst_reg dst,
                               src_reg src,
@@ -402,12 +450,12 @@ public:
    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
    void visit_instructions(const exec_list *list);
 
-   void emit_bool_to_cond_code(ir_rvalue *ir);
+   void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
    void emit_if_gen6(ir_if *ir);
 
    void emit_block_move(dst_reg *dst, src_reg *src,
-                       const struct glsl_type *type, bool predicated);
+                       const struct glsl_type *type, uint32_t predicate);
 
    void emit_constant_values(dst_reg *dst, ir_constant *value);
 
@@ -432,12 +480,16 @@ public:
    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 
-   int emit_vue_header_gen6(int header_mrf);
-   int emit_vue_header_gen4(int header_mrf);
+   void emit_ndc_computation();
+   void emit_psiz_and_flags(struct brw_reg reg);
+   void emit_clip_distances(struct brw_reg reg, int offset);
+   void emit_urb_slot(int mrf, int vert_result);
    void emit_urb_writes(void);
 
    src_reg get_scratch_offset(vec4_instruction *inst,
                              src_reg *reladdr, int reg_offset);
+   src_reg get_pull_constant_offset(vec4_instruction *inst,
+                                   src_reg *reladdr, int reg_offset);
    void emit_scratch_read(vec4_instruction *inst,
                          dst_reg dst,
                          src_reg orig_src,
@@ -446,6 +498,10 @@ public:
                           src_reg temp,
                           dst_reg orig_dst,
                           int base_offset);
+   void emit_pull_constant_load(vec4_instruction *inst,
+                               dst_reg dst,
+                               src_reg orig_src,
+                               int base_offset);
 
    GLboolean try_emit_sat(ir_expression *ir);
 
@@ -481,6 +537,9 @@ public:
    void generate_scratch_read(vec4_instruction *inst,
                              struct brw_reg dst,
                              struct brw_reg index);
+   void generate_pull_constant_load(vec4_instruction *inst,
+                                   struct brw_reg dst,
+                                   struct brw_reg index);
 };
 
 } /* namespace brw */