#ifdef __cplusplus
}; /* extern "C" */
+#include "gen8_generator.h"
#endif
#include "glsl/ir.h"
-struct brw_vs_compile;
-
struct brw_vec4_compile {
GLuint last_scratch; /**< measured in 32-byte (register size) units */
*/
GLuint nr_userclip_plane_consts:4;
- /**
- * True if the shader uses gl_ClipDistance, regardless of whether any clip
- * flags are enabled.
- */
- GLuint uses_clip_distance:1;
-
GLuint clamp_vertex_color:1;
struct brw_sampler_prog_key_data tex;
extern "C" {
#endif
+void
+brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
+ struct brw_vec4_prog_key *key,
+ GLuint id, struct gl_program *prog);
bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
const struct brw_vec4_prog_data *b);
void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
class reg
{
public:
- /** Register file: ARF, GRF, MRF, IMM. */
+ /** Register file: GRF, MRF, IMM. */
enum register_file file;
/** virtual register number. 0 = fixed hw reg */
int reg;
class src_reg : public reg
{
public:
- /* Callers of this ralloc-based new need not call delete. It's
- * easier to just ralloc_free 'ctx' (or any of its ancestors). */
- static void* operator new(size_t size, void *ctx)
- {
- void *node;
-
- node = ralloc_size(ctx, size);
- assert(node != NULL);
-
- return node;
- }
+ DECLARE_RALLOC_CXX_OPERATORS(src_reg)
void init();
class dst_reg : public reg
{
public:
- /* Callers of this ralloc-based new need not call delete. It's
- * easier to just ralloc_free 'ctx' (or any of its ancestors). */
- static void* operator new(size_t size, void *ctx)
- {
- void *node;
-
- node = ralloc_size(ctx, size);
- assert(node != NULL);
-
- return node;
- }
+ DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
void init();
src_reg *reladdr;
};
+dst_reg
+with_writemask(dst_reg const &r, int mask);
+
class vec4_instruction : public backend_instruction {
public:
- /* Callers of this ralloc-based new need not call delete. It's
- * easier to just ralloc_free 'ctx' (or any of its ancestors). */
- static void* operator new(size_t size, void *ctx)
- {
- void *node;
-
- node = rzalloc_size(ctx, size);
- assert(node != NULL);
-
- return node;
- }
+ DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
vec4_instruction(vec4_visitor *v, enum opcode opcode,
dst_reg dst = dst_reg(),
src_reg src2 = src_reg());
struct brw_reg get_dst(void);
- struct brw_reg get_src(int i);
+ struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
dst_reg dst;
src_reg src[3];
int target; /**< MRT target. */
bool shadow_compare;
- bool eot;
+ enum brw_urb_write_flags urb_write_flags;
bool header_present;
int mlen; /**< SEND message length */
int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
struct gl_shader_program *shader_prog,
struct brw_shader *shader,
void *mem_ctx,
- bool debug_flag);
+ bool debug_flag,
+ bool no_spills,
+ shader_time_shader_type st_base,
+ shader_time_shader_type st_written,
+ shader_time_shader_type st_reset);
~vec4_visitor();
dst_reg dst_null_f()
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
}
- struct gl_program *prog;
+ dst_reg dst_null_ud()
+ {
+ return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
+ }
+
struct brw_vec4_compile *c;
const struct brw_vec4_prog_key *key;
struct brw_vec4_prog_data *prog_data;
void setup_uniform_values(ir_variable *ir);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_uniforms(int payload_reg);
- void setup_payload();
bool reg_allocate_trivial();
bool reg_allocate();
void evaluate_spill_costs(float *spill_costs, bool *no_spill);
void split_uniform_registers();
void pack_uniform_registers();
void calculate_live_intervals();
+ void invalidate_live_intervals();
void split_virtual_grfs();
bool dead_code_eliminate();
bool virtual_grf_interferes(int a, int b);
vec4_instruction *emit(enum opcode opcode);
+ vec4_instruction *emit(enum opcode opcode, dst_reg dst);
+
vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
vec4_instruction *emit(enum opcode opcode, dst_reg dst,
vec4_instruction *FBH(dst_reg dst, src_reg value);
vec4_instruction *FBL(dst_reg dst, src_reg value);
vec4_instruction *CBIT(dst_reg dst, src_reg value);
+ vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
+ vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
+ vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
int implied_mrf_writes(vec4_instruction *inst);
void emit_pack_half_2x16(dst_reg dst, src_reg src0);
void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
+ uint32_t gather_channel(ir_texture *ir, int sampler);
+ src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
void emit_ndc_computation();
void emit_shader_time_write(enum shader_time_shader_type type,
src_reg value);
+ void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
+ dst_reg dst, src_reg offset, src_reg src0,
+ src_reg src1);
+
+ void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
+ src_reg offset);
+
src_reg get_scratch_offset(vec4_instruction *inst,
src_reg *reladdr, int reg_offset);
src_reg get_pull_constant_offset(vec4_instruction *inst,
void dump_instruction(backend_instruction *inst);
+ void visit_atomic_counter_intrinsic(ir_call *ir);
+
protected:
void emit_vertex();
- void lower_attributes_to_hw_regs(const int *attribute_map);
+ void lower_attributes_to_hw_regs(const int *attribute_map,
+ bool interleaved);
+ void setup_payload_interference(struct ra_graph *g, int first_payload_node,
+ int reg_node_count);
virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
- virtual int setup_attributes(int payload_reg) = 0;
+ virtual void setup_payload() = 0;
virtual void emit_prolog() = 0;
virtual void emit_program_code() = 0;
virtual void emit_thread_end() = 0;
virtual int compute_array_stride(ir_dereference_array *ir);
const bool debug_flag;
-};
-
-class vec4_vs_visitor : public vec4_visitor
-{
-public:
- vec4_vs_visitor(struct brw_context *brw,
- struct brw_vs_compile *vs_compile,
- struct brw_vs_prog_data *vs_prog_data,
- struct gl_shader_program *prog,
- struct brw_shader *shader,
- void *mem_ctx);
-
-protected:
- virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
- virtual int setup_attributes(int payload_reg);
- virtual void emit_prolog();
- virtual void emit_program_code();
- virtual void emit_thread_end();
- virtual void emit_urb_write_header(int mrf);
- virtual vec4_instruction *emit_urb_write_opcode(bool complete);
private:
- void setup_vp_regs();
- dst_reg get_vp_dst_reg(const prog_dst_register &dst);
- src_reg get_vp_src_reg(const prog_src_register &src);
-
- struct brw_vs_compile * const vs_compile;
- struct brw_vs_prog_data * const vs_prog_data;
- src_reg *vp_temp_regs;
- src_reg vp_addr_reg;
+ /**
+ * If true, then register allocation should fail instead of spilling.
+ */
+ const bool no_spills;
+
+ const shader_time_shader_type st_base;
+ const shader_time_shader_type st_written;
+ const shader_time_shader_type st_reset;
};
+
/**
* The vertex shader code generator.
*
struct brw_reg dst,
struct brw_reg src);
- void generate_urb_write(vec4_instruction *inst);
+ void generate_vs_urb_write(vec4_instruction *inst);
+ void generate_gs_urb_write(vec4_instruction *inst);
+ void generate_gs_thread_end(vec4_instruction *inst);
+ void generate_gs_set_write_offset(struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
+ void generate_gs_set_vertex_count(struct brw_reg dst,
+ struct brw_reg src);
+ void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+ void generate_gs_prepare_channel_masks(struct brw_reg dst);
+ void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
void generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index);
void generate_scratch_write(vec4_instruction *inst,
void generate_unpack_flags(vec4_instruction *inst,
struct brw_reg dst);
+ void generate_untyped_atomic(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg atomic_op,
+ struct brw_reg surf_index);
+
+ void generate_untyped_surface_read(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg surf_index);
+
void mark_surface_used(unsigned surf_index);
struct brw_context *brw;
- struct gl_context *ctx;
struct brw_compile *p;
const bool debug_flag;
};
+/**
+ * The vertex shader code generator.
+ *
+ * Translates VS IR to actual i965 assembly code.
+ */
+class gen8_vec4_generator : public gen8_generator
+{
+public:
+ gen8_vec4_generator(struct brw_context *brw,
+ struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
+ struct brw_vec4_prog_data *prog_data,
+ void *mem_ctx,
+ bool debug_flag);
+ ~gen8_vec4_generator();
+
+ const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+
+private:
+ void generate_code(exec_list *instructions);
+ void generate_vec4_instruction(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg *src);
+
+ void generate_tex(vec4_instruction *inst,
+ struct brw_reg dst);
+
+ void generate_urb_write(vec4_instruction *ir, bool copy_g0);
+ void generate_gs_thread_end(vec4_instruction *ir);
+ void generate_gs_set_write_offset(struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
+ void generate_gs_set_vertex_count(struct brw_reg dst,
+ struct brw_reg src);
+ void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+ void generate_gs_prepare_channel_masks(struct brw_reg dst);
+ void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
+
+ void generate_oword_dual_block_offsets(struct brw_reg m1,
+ struct brw_reg index);
+ void generate_scratch_write(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src,
+ struct brw_reg index);
+ void generate_scratch_read(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg index);
+ void generate_pull_constant_load(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg index,
+ struct brw_reg offset);
+
+ void mark_surface_used(unsigned surf_index);
+
+ struct brw_vec4_prog_data *prog_data;
+
+ const bool debug_flag;
+};
+
+
} /* namespace brw */
#endif /* __cplusplus */
projects / mesa.git / blobdiff