i965: Use sample barycentric coordinates with per sample shading

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 5cec9f930e383b5c445364eaa85275c5b43e1104..4a5b57775c30abea3bb29aaacbf96267b7b49176 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -39,6 +39,7 @@ extern "C" {
 
 #ifdef __cplusplus
 }; /* extern "C" */
+#include "gen8_generator.h"
 #endif
 
 #include "glsl/ir.h"
@@ -231,7 +232,10 @@ public:
                struct brw_shader *shader,
                void *mem_ctx,
                 bool debug_flag,
-                bool no_spills);
+                bool no_spills,
+                shader_time_shader_type st_base,
+                shader_time_shader_type st_written,
+                shader_time_shader_type st_reset);
    ~vec4_visitor();
 
    dst_reg dst_null_f()
@@ -477,6 +481,7 @@ public:
    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 
    uint32_t gather_channel(ir_texture *ir, int sampler);
+   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 
    void emit_ndc_computation();
@@ -546,6 +551,10 @@ private:
     * If true, then register allocation should fail instead of spilling.
     */
    const bool no_spills;
+
+   const shader_time_shader_type st_base;
+   const shader_time_shader_type st_written;
+   const shader_time_shader_type st_reset;
 };
 
 
@@ -652,6 +661,66 @@ private:
    const bool debug_flag;
 };
 
+/**
+ * The vertex shader code generator.
+ *
+ * Translates VS IR to actual i965 assembly code.
+ */
+class gen8_vec4_generator : public gen8_generator
+{
+public:
+   gen8_vec4_generator(struct brw_context *brw,
+                       struct gl_shader_program *shader_prog,
+                       struct gl_program *prog,
+                       struct brw_vec4_prog_data *prog_data,
+                       void *mem_ctx,
+                       bool debug_flag);
+   ~gen8_vec4_generator();
+
+   const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+
+private:
+   void generate_code(exec_list *instructions);
+   void generate_vec4_instruction(vec4_instruction *inst,
+                                  struct brw_reg dst,
+                                  struct brw_reg *src);
+
+   void generate_tex(vec4_instruction *inst,
+                     struct brw_reg dst);
+
+   void generate_urb_write(vec4_instruction *ir, bool copy_g0);
+   void generate_gs_thread_end(vec4_instruction *ir);
+   void generate_gs_set_write_offset(struct brw_reg dst,
+                                     struct brw_reg src0,
+                                     struct brw_reg src1);
+   void generate_gs_set_vertex_count(struct brw_reg dst,
+                                     struct brw_reg src);
+   void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+   void generate_gs_prepare_channel_masks(struct brw_reg dst);
+   void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
+
+   void generate_oword_dual_block_offsets(struct brw_reg m1,
+                                          struct brw_reg index);
+   void generate_scratch_write(vec4_instruction *inst,
+                               struct brw_reg dst,
+                               struct brw_reg src,
+                               struct brw_reg index);
+   void generate_scratch_read(vec4_instruction *inst,
+                              struct brw_reg dst,
+                              struct brw_reg index);
+   void generate_pull_constant_load(vec4_instruction *inst,
+                                    struct brw_reg dst,
+                                    struct brw_reg index,
+                                    struct brw_reg offset);
+
+   void mark_surface_used(unsigned surf_index);
+
+   struct brw_vec4_prog_data *prog_data;
+
+   const bool debug_flag;
+};
+
+
 } /* namespace brw */
 #endif /* __cplusplus */