#endif
#include "glsl/ir.h"
+#include "glsl/nir/nir.h"
-struct brw_vec4_compile {
- GLuint last_scratch; /**< measured in 32-byte (register size) units */
-};
-
#ifdef __cplusplus
extern "C" {
#endif
* Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
* fixed-function) into VS IR.
*/
-class vec4_visitor : public backend_visitor
+class vec4_visitor : public backend_shader, public ir_visitor
{
public:
- vec4_visitor(struct brw_context *brw,
- struct brw_vec4_compile *c,
+ vec4_visitor(const struct brw_compiler *compiler,
+ void *log_data,
struct gl_program *prog,
const struct brw_vue_prog_key *key,
struct brw_vue_prog_data *prog_data,
struct gl_shader_program *shader_prog,
gl_shader_stage stage,
void *mem_ctx,
- bool debug_flag,
bool no_spills,
- shader_time_shader_type st_base,
- shader_time_shader_type st_written,
- shader_time_shader_type st_reset);
+ int shader_time_index);
~vec4_visitor();
dst_reg dst_null_f()
return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
}
- struct brw_vec4_compile * const c;
const struct brw_vue_prog_key * const key;
struct brw_vue_prog_data * const prog_data;
unsigned int sanity_param_count;
virtual void visit(ir_if *);
virtual void visit(ir_emit_vertex *);
virtual void visit(ir_end_primitive *);
+ virtual void visit(ir_barrier *);
/*@}*/
src_reg result;
struct hash_table *variable_ht;
- bool run(void);
+ bool run(gl_clip_plane *clip_planes);
void fail(const char *msg, ...);
- void setup_uniform_clipplane_values();
+ void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
+ virtual void setup_vector_uniform_values(const gl_constant_value *values,
+ unsigned n);
void setup_uniform_values(ir_variable *ir);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_uniforms(int payload_reg);
+
bool reg_allocate_trivial();
bool reg_allocate();
void evaluate_spill_costs(float *spill_costs, bool *no_spill);
bool opt_vector_float();
bool opt_reduce_swizzle();
bool dead_code_eliminate();
+ int var_range_start(unsigned v, unsigned n) const;
+ int var_range_end(unsigned v, unsigned n) const;
bool virtual_grf_interferes(int a, int b);
bool opt_copy_propagation(bool do_constant_prop = true);
bool opt_cse_local(bblock_t *block);
bool opt_cse();
bool opt_algebraic();
bool opt_register_coalesce();
+ bool eliminate_find_live_channel();
bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
void opt_set_dependency_control();
void opt_schedule_instructions();
vec4_instruction *IF(src_reg src0, src_reg src1,
enum brw_conditional_mod condition);
vec4_instruction *IF(enum brw_predicate predicate);
- EMIT1(PULL_CONSTANT_LOAD)
EMIT1(SCRATCH_READ)
EMIT2(SCRATCH_WRITE)
EMIT3(LRP)
void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
void emit_if_gen6(ir_if *ir);
- void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
- src_reg src0, src_reg src1);
+ vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
+ src_reg src0, src_reg src1);
- void emit_lrp(const dst_reg &dst,
- const src_reg &x, const src_reg &y, const src_reg &a);
+ vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
+ const src_reg &y, const src_reg &a);
+
+ /**
+ * Copy any live channel from \p src to the first channel of the
+ * result.
+ */
+ src_reg emit_uniformize(const src_reg &src);
void emit_block_move(dst_reg *dst, src_reg *src,
const struct glsl_type *type, brw_predicate predicate);
void emit_scalar(ir_instruction *ir, enum prog_opcode op,
dst_reg dst, src_reg src0, src_reg src1);
- void emit_scs(ir_instruction *ir, enum prog_opcode op,
- dst_reg dst, const src_reg &src);
-
src_reg fix_3src_operand(src_reg src);
- void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
- const src_reg &src1 = src_reg());
+ vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
+ const src_reg &src1 = src_reg());
+
src_reg fix_math_operand(src_reg src);
void emit_pack_half_2x16(dst_reg dst, src_reg src0);
void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
- src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
+ src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
+ src_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
void emit_shader_time_begin();
void emit_shader_time_end();
- void emit_shader_time_write(enum shader_time_shader_type type,
- src_reg value);
+ void emit_shader_time_write(int shader_time_subindex, src_reg value);
void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
dst_reg dst, src_reg offset, src_reg src0,
dst_reg dst,
src_reg orig_src,
int base_offset);
+ void emit_pull_constant_load_reg(dst_reg dst,
+ src_reg surf_index,
+ src_reg offset,
+ bblock_t *before_block,
+ vec4_instruction *before_inst);
+ src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
+ vec4_instruction *inst, src_reg src);
bool try_emit_mad(ir_expression *ir);
bool try_emit_b2f_of_compare(ir_expression *ir);
void visit_atomic_counter_intrinsic(ir_call *ir);
+ int type_size(const struct glsl_type *type);
+ bool is_high_sampler(src_reg sampler);
+
+ virtual void emit_nir_code();
+ virtual void nir_setup_inputs(nir_shader *shader);
+ virtual void nir_setup_uniforms(nir_shader *shader);
+ virtual void nir_setup_uniform(nir_variable *var);
+ virtual void nir_setup_builtin_uniform(nir_variable *var);
+ virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
+ virtual void nir_setup_system_values(nir_shader *shader);
+ virtual void nir_emit_impl(nir_function_impl *impl);
+ virtual void nir_emit_cf_list(exec_list *list);
+ virtual void nir_emit_if(nir_if *if_stmt);
+ virtual void nir_emit_loop(nir_loop *loop);
+ virtual void nir_emit_block(nir_block *block);
+ virtual void nir_emit_instr(nir_instr *instr);
+ virtual void nir_emit_load_const(nir_load_const_instr *instr);
+ virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
+ virtual void nir_emit_alu(nir_alu_instr *instr);
+ virtual void nir_emit_jump(nir_jump_instr *instr);
+ virtual void nir_emit_texture(nir_tex_instr *instr);
+
+ dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
+ dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
+ dst_reg get_nir_dest(nir_dest dest);
+ src_reg get_nir_src(nir_src src, enum brw_reg_type type,
+ unsigned num_components = 4);
+ src_reg get_nir_src(nir_src src, nir_alu_type type,
+ unsigned num_components = 4);
+ src_reg get_nir_src(nir_src src,
+ unsigned num_components = 4);
+
+ virtual dst_reg *make_reg_for_system_value(int location,
+ const glsl_type *type) = 0;
+
+ dst_reg *nir_locals;
+ dst_reg *nir_ssa_values;
+ src_reg *nir_inputs;
+ unsigned *nir_uniform_driver_location;
+ dst_reg *nir_system_values;
+
protected:
void emit_vertex();
void lower_attributes_to_hw_regs(const int *attribute_map,
bool interleaved);
void setup_payload_interference(struct ra_graph *g, int first_payload_node,
int reg_node_count);
- virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
virtual void assign_binding_table_offsets();
virtual void setup_payload() = 0;
virtual void emit_prolog() = 0;
virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
virtual int compute_array_stride(ir_dereference_array *ir);
- const bool debug_flag;
-
private:
/**
* If true, then register allocation should fail instead of spilling.
*/
const bool no_spills;
- const shader_time_shader_type st_base;
- const shader_time_shader_type st_written;
- const shader_time_shader_type st_reset;
+ int shader_time_index;
+
+ unsigned last_scratch; /**< measured in 32-byte (register size) units */
};
class vec4_generator
{
public:
- vec4_generator(struct brw_context *brw,
+ vec4_generator(const struct brw_compiler *compiler, void *log_data,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_vue_prog_data *prog_data,
struct brw_reg dst,
struct brw_reg surf_index,
struct brw_reg offset);
- void generate_unpack_flags(vec4_instruction *inst,
- struct brw_reg dst);
-
- void generate_untyped_atomic(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg atomic_op,
- struct brw_reg surf_index);
+ void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
+ struct brw_reg dst);
+ void generate_unpack_flags(struct brw_reg dst);
- void generate_untyped_surface_read(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg surf_index);
+ const struct brw_compiler *compiler;
+ void *log_data; /* Passed to compiler->*_log functions */
- struct brw_context *brw;
+ const struct brw_device_info *devinfo;
- struct brw_compile *p;
+ struct brw_codegen *p;
struct gl_shader_program *shader_prog;
const struct gl_program *prog;
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