class dst_reg;
-/**
- * Common helper for constructing swizzles. When only a subset of
- * channels of a vec4 are used, we don't want to reference the other
- * channels, as that will tell optimization passes that those other
- * channels are used.
- */
-static int
-swizzle_for_size(int size)
-{
- int size_swizzles[4] = {
- BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
- BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
- BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
- BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
- };
-
- assert((size >= 1) && (size <= 4));
- return size_swizzles[size - 1];
-}
+unsigned
+swizzle_for_size(int size);
enum register_file {
ARF = BRW_ARCHITECTURE_REGISTER_FILE,
return node;
}
- void init()
- {
- memset(this, 0, sizeof(*this));
-
- this->file = BAD_FILE;
- }
-
- src_reg(register_file file, int reg, const glsl_type *type)
- {
- init();
-
- this->file = file;
- this->reg = reg;
- if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
- this->swizzle = swizzle_for_size(type->vector_elements);
- else
- this->swizzle = SWIZZLE_XYZW;
- }
-
- /** Generic unset register constructor. */
- src_reg()
- {
- init();
- }
-
- src_reg(float f)
- {
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_F;
- this->imm.f = f;
- }
-
- src_reg(uint32_t u)
- {
- init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_UD;
- this->imm.f = u;
- }
-
- src_reg(int32_t i)
- {
- init();
+ void init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_D;
- this->imm.i = i;
- }
+ src_reg(register_file file, int reg, const glsl_type *type);
+ src_reg();
+ src_reg(float f);
+ src_reg(uint32_t u);
+ src_reg(int32_t i);
bool equals(src_reg *r);
bool is_zero() const;
return node;
}
- void init()
- {
- memset(this, 0, sizeof(*this));
- this->file = BAD_FILE;
- this->writemask = WRITEMASK_XYZW;
- }
-
- dst_reg()
- {
- init();
- }
-
- dst_reg(register_file file, int reg)
- {
- init();
-
- this->file = file;
- this->reg = reg;
- }
-
- dst_reg(struct brw_reg reg)
- {
- init();
-
- this->file = HW_REG;
- this->fixed_hw_reg = reg;
- }
+ void init();
+ dst_reg();
+ dst_reg(register_file file, int reg);
+ dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
+ dst_reg(struct brw_reg reg);
dst_reg(class vec4_visitor *v, const struct glsl_type *type);
explicit dst_reg(src_reg reg);
int conditional_mod; /**< BRW_CONDITIONAL_* */
int sampler;
+ uint32_t texture_offset; /**< Texture Offset bitfield */
int target; /**< MRT target. */
bool shadow_compare;
ir_instruction *ir;
const char *annotation;
+ bool is_tex();
bool is_math();
};
int virtual_grf_count;
int virtual_grf_array_size;
int first_non_payload_grf;
+ unsigned int max_grf;
int *virtual_grf_def;
int *virtual_grf_use;
+ dst_reg userplane[MAX_CLIP_PLANES];
/**
* This is the size to be used for an array with an element per
void fail(const char *msg, ...);
int virtual_grf_alloc(int size);
+ void setup_uniform_clipplane_values();
int setup_uniform_values(int loc, const glsl_type *type);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_attributes(int payload_reg);
int setup_uniforms(int payload_reg);
void setup_payload();
- void reg_allocate_trivial();
- void reg_allocate();
+ bool reg_allocate_trivial();
+ bool reg_allocate();
+ void evaluate_spill_costs(float *spill_costs, bool *no_spill);
+ int choose_spill_reg(struct ra_graph *g);
+ void spill_reg(int spill_reg);
void move_grf_array_access_to_scratch();
void move_uniform_array_access_to_pull_constants();
void move_push_constants_to_pull_constants();
void split_uniform_registers();
void pack_uniform_registers();
void calculate_live_intervals();
+ void split_virtual_grfs();
bool dead_code_eliminate();
bool virtual_grf_interferes(int a, int b);
bool opt_copy_propagation();
bool opt_algebraic();
+ bool opt_compute_to_mrf();
vec4_instruction *emit(vec4_instruction *inst);
void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
+ void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
+
void emit_ndc_computation();
void emit_psiz_and_flags(struct brw_reg reg);
void emit_clip_distances(struct brw_reg reg, int offset);
+ void emit_generic_urb_slot(dst_reg reg, int vert_result);
void emit_urb_slot(int mrf, int vert_result);
void emit_urb_writes(void);
src_reg orig_src,
int base_offset);
- GLboolean try_emit_sat(ir_expression *ir);
+ bool try_emit_sat(ir_expression *ir);
+ void resolve_ud_negate(src_reg *reg);
bool process_move_condition(ir_rvalue *ir);
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
+ void generate_math2_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1);
+
+ void generate_tex(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src);
void generate_urb_write(vec4_instruction *inst);
void generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index);
void generate_pull_constant_load(vec4_instruction *inst,
struct brw_reg dst,
- struct brw_reg index);
+ struct brw_reg index,
+ struct brw_reg offset);
+
+ void dump_instruction(vec4_instruction *inst);
+ void dump_instructions();
};
} /* namespace brw */
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