intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 833bef17d0e2ceecde709e295cc9029f4804dd5e..e9701629340e3e49469b404697898ea0eaf01f43 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -28,15 +28,67 @@
 #include "brw_shader.h"
 #include "main/compiler.h"
 #include "program/hash_table.h"
+#include "brw_program.h"
 
+#ifdef __cplusplus
 extern "C" {
-#include "brw_vs.h"
+#endif
+
 #include "brw_context.h"
 #include "brw_eu.h"
-};
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
 
 #include "glsl/ir.h"
 
+struct brw_vs_compile;
+
+
+struct brw_vec4_compile {
+   GLuint last_scratch; /**< measured in 32-byte (register size) units */
+};
+
+
+struct brw_vec4_prog_key {
+   GLuint program_string_id;
+
+   /**
+    * True if at least one clip flag is enabled, regardless of whether the
+    * shader uses clip planes or gl_ClipDistance.
+    */
+   GLuint userclip_active:1;
+
+   /**
+    * How many user clipping planes are being uploaded to the vertex shader as
+    * push constants.
+    */
+   GLuint nr_userclip_plane_consts:4;
+
+   /**
+    * True if the shader uses gl_ClipDistance, regardless of whether any clip
+    * flags are enabled.
+    */
+   GLuint uses_clip_distance:1;
+
+   GLuint clamp_vertex_color:1;
+
+   struct brw_sampler_prog_key_data tex;
+};
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
+                                const struct brw_vec4_prog_data *b);
+void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
+
+#ifdef __cplusplus
+} /* extern "C" */
+
 namespace brw {
 
 class dst_reg;
@@ -154,7 +206,7 @@ public:
                    src_reg src2 = src_reg());
 
    struct brw_reg get_dst(void);
-   struct brw_reg get_src(int i);
+   struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 
    dst_reg dst;
    src_reg src[3];
@@ -170,7 +222,7 @@ public:
    int target; /**< MRT target. */
    bool shadow_compare;
 
-   bool eot;
+   enum brw_urb_write_flags urb_write_flags;
    bool header_present;
    int mlen; /**< SEND message length */
    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
@@ -315,7 +367,6 @@ public:
    void setup_uniform_values(ir_variable *ir);
    void setup_builtin_uniform_values(ir_variable *ir);
    int setup_uniforms(int payload_reg);
-   void setup_payload();
    bool reg_allocate_trivial();
    bool reg_allocate();
    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
@@ -389,6 +440,7 @@ public:
    vec4_instruction *FBH(dst_reg dst, src_reg value);
    vec4_instruction *FBL(dst_reg dst, src_reg value);
    vec4_instruction *CBIT(dst_reg dst, src_reg value);
+   vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
 
    int implied_mrf_writes(vec4_instruction *inst);
 
@@ -486,8 +538,10 @@ public:
 protected:
    void emit_vertex();
    void lower_attributes_to_hw_regs(const int *attribute_map);
+   void setup_payload_interference(struct ra_graph *g, int first_payload_node,
+                                   int reg_node_count);
    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
-   virtual int setup_attributes(int payload_reg) = 0;
+   virtual void setup_payload() = 0;
    virtual void emit_prolog() = 0;
    virtual void emit_program_code() = 0;
    virtual void emit_thread_end() = 0;
@@ -510,7 +564,7 @@ public:
 
 protected:
    virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
-   virtual int setup_attributes(int payload_reg);
+   virtual void setup_payload();
    virtual void emit_prolog();
    virtual void emit_program_code();
    virtual void emit_thread_end();
@@ -518,6 +572,7 @@ protected:
    virtual vec4_instruction *emit_urb_write_opcode(bool complete);
 
 private:
+   int setup_attributes(int payload_reg);
    void setup_vp_regs();
    dst_reg get_vp_dst_reg(const prog_dst_register &dst);
    src_reg get_vp_src_reg(const prog_src_register &src);
@@ -575,7 +630,15 @@ private:
                     struct brw_reg dst,
                     struct brw_reg src);
 
-   void generate_urb_write(vec4_instruction *inst);
+   void generate_vs_urb_write(vec4_instruction *inst);
+   void generate_gs_urb_write(vec4_instruction *inst);
+   void generate_gs_thread_end(vec4_instruction *inst);
+   void generate_gs_set_write_offset(struct brw_reg dst,
+                                     struct brw_reg src0,
+                                     struct brw_reg src1);
+   void generate_gs_set_vertex_count(struct brw_reg dst,
+                                     struct brw_reg src);
+   void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
    void generate_oword_dual_block_offsets(struct brw_reg m1,
                                          struct brw_reg index);
    void generate_scratch_write(vec4_instruction *inst,
@@ -596,8 +659,9 @@ private:
    void generate_unpack_flags(vec4_instruction *inst,
                               struct brw_reg dst);
 
+   void mark_surface_used(unsigned surf_index);
+
    struct brw_context *brw;
-   struct gl_context *ctx;
 
    struct brw_compile *p;
 
@@ -612,5 +676,6 @@ private:
 };
 
 } /* namespace brw */
+#endif /* __cplusplus */
 
 #endif /* BRW_VEC4_H */