*/
#include "brw_vec4.h"
+#include "brw_cfg.h"
extern "C" {
#include "main/macros.h"
}
inst->dst.file == GRF &&
!inst->dst.reladdr &&
!inst->src[0].reladdr &&
- inst->dst.type == inst->src[0].type);
+ (inst->dst.type == inst->src[0].type ||
+ (inst->dst.type == BRW_REGISTER_TYPE_F &&
+ inst->src[0].type == BRW_REGISTER_TYPE_VF)));
}
static bool
inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
}
+static unsigned
+swizzle_vf_imm(unsigned vf4, unsigned swizzle)
+{
+ union {
+ unsigned vf4;
+ uint8_t vf[4];
+ } v = { vf4 }, ret;
+
+ ret.vf[0] = v.vf[BRW_GET_SWZ(swizzle, 0)];
+ ret.vf[1] = v.vf[BRW_GET_SWZ(swizzle, 1)];
+ ret.vf[2] = v.vf[BRW_GET_SWZ(swizzle, 2)];
+ ret.vf[3] = v.vf[BRW_GET_SWZ(swizzle, 3)];
+
+ return ret.vf4;
+}
+
+static bool
+is_logic_op(enum opcode opcode)
+{
+ return (opcode == BRW_OPCODE_AND ||
+ opcode == BRW_OPCODE_OR ||
+ opcode == BRW_OPCODE_XOR ||
+ opcode == BRW_OPCODE_NOT);
+}
+
static bool
try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
int arg, struct copy_entry *entry)
if (value.file != IMM)
return false;
+ if (value.type == BRW_REGISTER_TYPE_VF) {
+ /* The result of bit-casting the component values of a vector float
+ * cannot in general be represented as an immediate.
+ */
+ if (inst->src[arg].type != BRW_REGISTER_TYPE_F)
+ return false;
+ } else {
+ value.type = inst->src[arg].type;
+ }
+
if (inst->src[arg].abs) {
- if (value.type == BRW_REGISTER_TYPE_F) {
- value.fixed_hw_reg.dw1.f = fabs(value.fixed_hw_reg.dw1.f);
- } else if (value.type == BRW_REGISTER_TYPE_D) {
- if (value.fixed_hw_reg.dw1.d < 0)
- value.fixed_hw_reg.dw1.d = -value.fixed_hw_reg.dw1.d;
+ if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ !brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
+ return false;
}
}
if (inst->src[arg].negate) {
- if (value.type == BRW_REGISTER_TYPE_F)
- value.fixed_hw_reg.dw1.f = -value.fixed_hw_reg.dw1.f;
- else
- value.fixed_hw_reg.dw1.ud = -value.fixed_hw_reg.dw1.ud;
+ if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+ !brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
+ return false;
+ }
}
+ if (value.type == BRW_REGISTER_TYPE_VF)
+ value.fixed_hw_reg.dw1.ud = swizzle_vf_imm(value.fixed_hw_reg.dw1.ud,
+ inst->src[arg].swizzle);
+
switch (inst->opcode) {
case BRW_OPCODE_MOV:
inst->src[arg] = value;
return false;
}
-static bool
-is_logic_op(enum opcode opcode)
-{
- return (opcode == BRW_OPCODE_AND ||
- opcode == BRW_OPCODE_OR ||
- opcode == BRW_OPCODE_XOR ||
- opcode == BRW_OPCODE_NOT);
-}
-
static bool
try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
- int arg, struct copy_entry *entry, int reg)
+ int arg, struct copy_entry *entry)
{
/* For constant propagation, we only handle the same constant
* across all 4 channels. Some day, we should handle the 8-bit
inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
return false;
- bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
- inst->opcode == BRW_OPCODE_MAD ||
- inst->opcode == BRW_OPCODE_BFE ||
- inst->opcode == BRW_OPCODE_BFI2);
- if (is_3src_inst && value.file == UNIFORM)
+ if (inst->is_3src() && value.file == UNIFORM)
return false;
if (inst->is_send_from_grf())
return false;
- /* We can't copy-propagate a UD negation into a condmod
- * instruction, because the condmod ends up looking at the 33-bit
- * signed accumulator value instead of the 32-bit value we wanted
+ /* we can't generally copy-propagate UD negations becuse we
+ * end up accessing the resulting values as signed integers
+ * instead. See also resolve_ud_negate().
*/
- if (inst->conditional_mod &&
- value.negate &&
+ if (value.negate &&
value.type == BRW_REGISTER_TYPE_UD)
return false;
}
bool
-vec4_visitor::opt_copy_propagation()
+vec4_visitor::opt_copy_propagation(bool do_constant_prop)
{
bool progress = false;
- struct copy_entry entries[virtual_grf_reg_count];
+ struct copy_entry entries[alloc.total_size];
memset(&entries, 0, sizeof(entries));
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
/* This pass only works on basic blocks. If there's flow
* control, throw out all our information and start from
* scratch.
inst->src[i].reladdr)
continue;
- int reg = (virtual_grf_reg_map[inst->src[i].reg] +
+ int reg = (alloc.offsets[inst->src[i].reg] +
inst->src[i].reg_offset);
/* Find the regs that each swizzle component came from.
if (c != 4)
continue;
- if (try_constant_propagate(brw, inst, i, &entry))
+ if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
progress = true;
- if (try_copy_propagate(brw, inst, i, &entry, reg))
+ if (try_copy_propagate(brw, inst, i, &entry))
progress = true;
}
/* Track available source registers. */
if (inst->dst.file == GRF) {
const int reg =
- virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
+ alloc.offsets[inst->dst.reg] + inst->dst.reg_offset;
/* Update our destination's current channel values. For a direct copy,
* the value is the newly propagated source. Otherwise, we don't know
entries[reg].saturatemask = 0x0;
for (int i = 0; i < 4; i++) {
if (inst->dst.writemask & (1 << i)) {
- entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
+ entries[reg].value[i] = (!inst->saturate && direct_copy) ? &inst->src[0] : NULL;
entries[reg].saturatemask |= (((inst->saturate && direct_copy) ? 1 : 0) << i);
}
}
if (inst->dst.reladdr)
memset(&entries, 0, sizeof(entries));
else {
- for (int i = 0; i < virtual_grf_reg_count; i++) {
+ for (unsigned i = 0; i < alloc.total_size; i++) {
for (int j = 0; j < 4; j++) {
if (is_channel_updated(inst, entries[i].value, j)){
entries[i].value[j] = NULL;
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