inst->opcode != BRW_OPCODE_ENDIF);
}
+static bool
+is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
+{
+ const src_reg *src = values[ch];
+
+ /* consider GRF only */
+ assert(inst->dst.file == GRF);
+ if (!src || src->file != GRF)
+ return false;
+
+ return (src->reg == inst->dst.reg &&
+ src->reg_offset == inst->dst.reg_offset &&
+ inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
+}
+
static bool
try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
{
inst->src[arg] = value;
return true;
+ case BRW_OPCODE_DP2:
+ case BRW_OPCODE_DP3:
+ case BRW_OPCODE_DP4:
+ case BRW_OPCODE_DPH:
+ case BRW_OPCODE_BFI1:
+ case BRW_OPCODE_ASR:
+ case BRW_OPCODE_SHL:
+ case BRW_OPCODE_SHR:
+ case BRW_OPCODE_SUBB:
+ if (arg == 1) {
+ inst->src[arg] = value;
+ return true;
+ }
+ break;
+
+ case BRW_OPCODE_MACH:
case BRW_OPCODE_MUL:
case BRW_OPCODE_ADD:
+ case BRW_OPCODE_OR:
+ case BRW_OPCODE_AND:
+ case BRW_OPCODE_XOR:
+ case BRW_OPCODE_ADDC:
if (arg == 1) {
inst->src[arg] = value;
return true;
} else if (arg == 0 && inst->src[1].file != IMM) {
- /* Fit this constant in by commuting the operands */
+ /* Fit this constant in by commuting the operands. Exception: we
+ * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
+ */
+ if ((inst->opcode == BRW_OPCODE_MUL ||
+ inst->opcode == BRW_OPCODE_MACH) &&
+ (inst->src[1].type == BRW_REGISTER_TYPE_D ||
+ inst->src[1].type == BRW_REGISTER_TYPE_UD))
+ break;
inst->src[0] = inst->src[1];
inst->src[1] = value;
return true;
return false;
}
-static bool
-try_copy_propagation(struct intel_context *intel,
- vec4_instruction *inst, int arg, src_reg *values[4])
+bool
+vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
+ src_reg *values[4])
{
/* For constant propagation, we only handle the same constant
* across all 4 channels. Some day, we should handle the 8-bit
value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
if (value.file != UNIFORM &&
+ value.file != GRF &&
value.file != ATTR)
return false;
value.abs = true;
}
if (inst->src[arg].negate)
- value.negate = true;
+ value.negate = !value.negate;
+
+ bool has_source_modifiers = value.negate || value.abs;
+
+ /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
+ * instructions.
+ */
+ if ((has_source_modifiers || value.file == UNIFORM ||
+ value.swizzle != BRW_SWIZZLE_XYZW) && !can_do_source_mods(inst))
+ return false;
+
+ if (has_source_modifiers && value.type != inst->src[arg].type)
+ return false;
+
+ bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
+ inst->opcode == BRW_OPCODE_MAD ||
+ inst->opcode == BRW_OPCODE_BFE ||
+ inst->opcode == BRW_OPCODE_BFI2);
+ if (is_3src_inst && value.file == UNIFORM)
+ return false;
+
+ if (inst->is_send_from_grf())
+ return false;
- /* FINISHME: We can't copy-propagate things that aren't normal
- * vec8s into gen6 math instructions, because of the weird src
- * handling for those instructions. Just ignore them for now.
+ /* We can't copy-propagate a UD negation into a condmod
+ * instruction, because the condmod ends up looking at the 33-bit
+ * signed accumulator value instead of the 32-bit value we wanted
*/
- if (intel->gen >= 6 && inst->is_math())
+ if (inst->conditional_mod &&
+ value.negate &&
+ value.type == BRW_REGISTER_TYPE_UD)
return false;
+ /* Don't report progress if this is a noop. */
+ if (value.equals(&inst->src[arg]))
+ return false;
+
+ value.type = inst->src[arg].type;
inst->src[arg] = value;
return true;
}
* optimizing out access to the copy result
*/
for (int i = 2; i >= 0; i--) {
- int reg = (virtual_grf_reg_map[inst->src[i].reg] +
- inst->src[i].reg_offset);
-
/* Copied values end up in GRFs, and we don't track reladdr
* accesses.
*/
inst->src[i].reladdr)
continue;
+ int reg = (virtual_grf_reg_map[inst->src[i].reg] +
+ inst->src[i].reg_offset);
+
/* Find the regs that each swizzle component came from.
*/
src_reg *values[4];
continue;
if (try_constant_propagation(inst, i, values) ||
- try_copy_propagation(intel, inst, i, values))
+ try_copy_propagation(inst, i, values))
progress = true;
}
/* Track available source registers. */
- if (is_direct_copy(inst)) {
- int reg = virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
+ if (inst->dst.file == GRF) {
+ const int reg =
+ virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
+
+ /* Update our destination's current channel values. For a direct copy,
+ * the value is the newly propagated source. Otherwise, we don't know
+ * the new value, so clear it.
+ */
+ bool direct_copy = is_direct_copy(inst);
for (int i = 0; i < 4; i++) {
if (inst->dst.writemask & (1 << i)) {
- cur_value[reg][i] = &inst->src[0];
+ cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
}
}
- continue;
- }
- /* For any updated channels, clear tracking of them as a source
- * or destination.
- *
- * FINISHME: Sources aren't handled, which will need to be done
- * for copy propagation.
- */
- if (inst->dst.file == GRF) {
+ /* Clear the records for any registers whose current value came from
+ * our destination's updated channels, as the two are no longer equal.
+ */
if (inst->dst.reladdr)
memset(cur_value, 0, sizeof(cur_value));
else {
- int reg = virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
-
- for (int i = 0; i < 4; i++) {
- if (inst->dst.writemask & (1 << i))
- cur_value[reg][i] = NULL;
+ for (int i = 0; i < virtual_grf_reg_count; i++) {
+ for (int j = 0; j < 4; j++) {
+ if (is_channel_updated(inst, cur_value[i], j)){
+ cur_value[i][j] = NULL;
+ }
+ }
}
}
}
}
if (progress)
- live_intervals_valid = false;
+ invalidate_live_intervals();
return progress;
}
projects / mesa.git / blobdiff