*/
#include "brw_vec4.h"
+#include "brw_vec4_live_variables.h"
#include "brw_cfg.h"
using namespace brw;
case BRW_OPCODE_CMPN:
case BRW_OPCODE_ADD:
case BRW_OPCODE_MUL:
+ case SHADER_OPCODE_MULH:
case BRW_OPCODE_FRC:
case BRW_OPCODE_RNDU:
case BRW_OPCODE_RNDD:
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
case VEC4_OPCODE_UNPACK_UNIFORM:
+ case SHADER_OPCODE_FIND_LIVE_CHANNEL:
+ case SHADER_OPCODE_BROADCAST:
+ case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
+ case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
return true;
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
{
return a->opcode == b->opcode &&
a->saturate == b->saturate &&
+ a->predicate == b->predicate &&
+ a->predicate_inverse == b->predicate_inverse &&
a->conditional_mod == b->conditional_mod &&
+ a->flag_subreg == b->flag_subreg &&
a->dst.type == b->dst.type &&
+ a->offset == b->offset &&
+ a->mlen == b->mlen &&
+ a->base_mrf == b->base_mrf &&
+ a->header_size == b->header_size &&
+ a->shadow_compare == b->shadow_compare &&
a->dst.writemask == b->dst.writemask &&
- a->regs_written == b->regs_written &&
+ a->force_writemask_all == b->force_writemask_all &&
+ a->size_written == b->size_written &&
operands_match(a, b);
}
foreach_inst_in_block (vec4_instruction, inst, block) {
/* Skip some cases. */
if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
- (inst->dst.file != HW_REG || inst->dst.is_null()))
+ ((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
+ inst->dst.is_null()))
{
bool found = false;
*/
bool no_existing_temp = entry->tmp.file == BAD_FILE;
if (no_existing_temp && !entry->generator->dst.is_null()) {
- entry->tmp = retype(src_reg(GRF, alloc.allocate(
- entry->generator->regs_written),
+ entry->tmp = retype(src_reg(VGRF, alloc.allocate(
+ regs_written(entry->generator)),
NULL), inst->dst.type);
- for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
+ for (unsigned i = 0; i < regs_written(entry->generator); ++i) {
vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
offset(entry->tmp, i));
+ copy->force_writemask_all =
+ entry->generator->force_writemask_all;
entry->generator->insert_after(block, copy);
}
if (!inst->dst.is_null()) {
assert(inst->dst.type == entry->tmp.type);
- for (unsigned i = 0; i < inst->regs_written; ++i) {
+ for (unsigned i = 0; i < regs_written(inst); ++i) {
vec4_instruction *copy = MOV(offset(inst->dst, i),
offset(entry->tmp, i));
copy->force_writemask_all = inst->force_writemask_all;
* overwrote.
*/
if (inst->dst.file == entry->generator->src[i].file &&
- inst->dst.reg == entry->generator->src[i].reg) {
+ inst->dst.nr == entry->generator->src[i].nr) {
entry->remove();
ralloc_free(entry);
break;
/* Kill any AEB entries using registers that don't get reused any
* more -- a sure sign they'll fail operands_match().
*/
- if (src->file == GRF) {
- assert((unsigned)(src->reg * 4 + 3) < (alloc.count * 4));
-
- int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
- virtual_grf_end[src->reg * 4 + 1]),
- MAX2(virtual_grf_end[src->reg * 4 + 2],
- virtual_grf_end[src->reg * 4 + 3]));
- if (last_reg_use < ip) {
+ if (src->file == VGRF) {
+ if (var_range_end(var_from_reg(alloc, dst_reg(*src)), 4) < ip) {
entry->remove();
ralloc_free(entry);
break;