*/
#include "brw_vec4.h"
+#include "brw_vec4_live_variables.h"
#include "brw_cfg.h"
using namespace brw;
is_expression(const vec4_instruction *const inst)
{
switch (inst->opcode) {
+ case BRW_OPCODE_MOV:
case BRW_OPCODE_SEL:
case BRW_OPCODE_NOT:
case BRW_OPCODE_AND:
case BRW_OPCODE_SHR:
case BRW_OPCODE_SHL:
case BRW_OPCODE_ASR:
+ case BRW_OPCODE_CMP:
+ case BRW_OPCODE_CMPN:
case BRW_OPCODE_ADD:
case BRW_OPCODE_MUL:
+ case SHADER_OPCODE_MULH:
case BRW_OPCODE_FRC:
case BRW_OPCODE_RNDU:
case BRW_OPCODE_RNDD:
case BRW_OPCODE_PLN:
case BRW_OPCODE_MAD:
case BRW_OPCODE_LRP:
+ case VEC4_OPCODE_UNPACK_UNIFORM:
+ case SHADER_OPCODE_FIND_LIVE_CHANNEL:
+ case SHADER_OPCODE_BROADCAST:
return true;
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
}
static bool
-is_expression_commutative(enum opcode op)
+operands_match(const vec4_instruction *a, const vec4_instruction *b)
{
- switch (op) {
- case BRW_OPCODE_AND:
- case BRW_OPCODE_OR:
- case BRW_OPCODE_XOR:
- case BRW_OPCODE_ADD:
- case BRW_OPCODE_MUL:
- return true;
- default:
- return false;
- }
-}
+ const src_reg *xs = a->src;
+ const src_reg *ys = b->src;
-static bool
-operands_match(enum opcode op, src_reg *xs, src_reg *ys)
-{
- if (!is_expression_commutative(op)) {
+ if (a->opcode == BRW_OPCODE_MAD) {
+ return xs[0].equals(ys[0]) &&
+ ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
+ (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
+ } else if (!a->is_commutative()) {
return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
} else {
return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
{
return a->opcode == b->opcode &&
a->saturate == b->saturate &&
+ a->predicate == b->predicate &&
+ a->predicate_inverse == b->predicate_inverse &&
a->conditional_mod == b->conditional_mod &&
+ a->flag_subreg == b->flag_subreg &&
a->dst.type == b->dst.type &&
+ a->offset == b->offset &&
+ a->mlen == b->mlen &&
+ a->base_mrf == b->base_mrf &&
+ a->header_size == b->header_size &&
+ a->shadow_compare == b->shadow_compare &&
a->dst.writemask == b->dst.writemask &&
- operands_match(a->opcode, a->src, b->src);
+ a->force_writemask_all == b->force_writemask_all &&
+ a->regs_written == b->regs_written &&
+ operands_match(a, b);
}
bool
-vec4_visitor::opt_cse_local(bblock_t *block, exec_list *aeb)
+vec4_visitor::opt_cse_local(bblock_t *block)
{
bool progress = false;
+ exec_list aeb;
void *cse_ctx = ralloc_context(NULL);
- for (vec4_instruction *inst = (vec4_instruction *)block->start;
- inst != block->end->next;
- inst = (vec4_instruction *) inst->next) {
-
+ int ip = block->start_ip;
+ foreach_inst_in_block (vec4_instruction, inst, block) {
/* Skip some cases. */
if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
- !inst->conditional_mod)
+ (inst->dst.file != HW_REG || inst->dst.is_null()))
{
bool found = false;
- foreach_in_list_use_after(aeb_entry, entry, aeb) {
+ foreach_in_list_use_after(aeb_entry, entry, &aeb) {
/* Match current instruction's expression against those in AEB. */
- if (instructions_match(inst, entry->generator)) {
+ if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
+ instructions_match(inst, entry->generator)) {
found = true;
progress = true;
break;
}
if (!found) {
- /* Our first sighting of this expression. Create an entry. */
- aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
- entry->tmp = src_reg(); /* file will be BAD_FILE */
- entry->generator = inst;
- aeb->push_tail(entry);
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ (inst->opcode == BRW_OPCODE_MOV &&
+ inst->src[0].file == IMM &&
+ inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
+ /* Our first sighting of this expression. Create an entry. */
+ aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
+ entry->tmp = src_reg(); /* file will be BAD_FILE */
+ entry->generator = inst;
+ aeb.push_tail(entry);
+ }
} else {
/* This is at least our second sighting of this expression.
* If we don't have a temporary already, make one.
*/
bool no_existing_temp = entry->tmp.file == BAD_FILE;
- if (no_existing_temp) {
- entry->tmp = src_reg(this, glsl_type::float_type);
- entry->tmp.type = inst->dst.type;
- entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
+ if (no_existing_temp && !entry->generator->dst.is_null()) {
+ entry->tmp = retype(src_reg(GRF, alloc.allocate(
+ entry->generator->regs_written),
+ NULL), inst->dst.type);
+
+ for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
+ vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
+ offset(entry->tmp, i));
+ copy->force_writemask_all =
+ entry->generator->force_writemask_all;
+ entry->generator->insert_after(block, copy);
+ }
- vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
- entry->generator->insert_after(copy);
entry->generator->dst = dst_reg(entry->tmp);
}
/* dest <- temp */
- assert(inst->dst.type == entry->tmp.type);
- vec4_instruction *copy = MOV(inst->dst, entry->tmp);
- copy->force_writemask_all = inst->force_writemask_all;
- inst->insert_before(copy);
+ if (!inst->dst.is_null()) {
+ assert(inst->dst.type == entry->tmp.type);
+
+ for (unsigned i = 0; i < inst->regs_written; ++i) {
+ vec4_instruction *copy = MOV(offset(inst->dst, i),
+ offset(entry->tmp, i));
+ copy->force_writemask_all = inst->force_writemask_all;
+ inst->insert_before(block, copy);
+ }
+ }
/* Set our iterator so that next time through the loop inst->next
* will get the instruction in the basic block after the one we've
*/
vec4_instruction *prev = (vec4_instruction *)inst->prev;
- inst->remove();
-
- /* Appending an instruction may have changed our bblock end. */
- if (inst == block->end) {
- block->end = prev;
- }
-
+ inst->remove(block);
inst = prev;
}
}
- foreach_in_list_safe(aeb_entry, entry, aeb) {
+ foreach_in_list_safe(aeb_entry, entry, &aeb) {
+ /* Kill all AEB entries that write a different value to or read from
+ * the flag register if we just wrote it.
+ */
+ if (inst->writes_flag()) {
+ if (entry->generator->reads_flag() ||
+ (entry->generator->writes_flag() &&
+ !instructions_match(inst, entry->generator))) {
+ entry->remove();
+ ralloc_free(entry);
+ continue;
+ }
+ }
+
for (int i = 0; i < 3; i++) {
+ src_reg *src = &entry->generator->src[i];
+
/* Kill all AEB entries that use the destination we just
* overwrote.
*/
ralloc_free(entry);
break;
}
+
+ /* Kill any AEB entries using registers that don't get reused any
+ * more -- a sure sign they'll fail operands_match().
+ */
+ if (src->file == GRF) {
+ if (var_range_end(var_from_reg(alloc, *src), 4) < ip) {
+ entry->remove();
+ ralloc_free(entry);
+ break;
+ }
+ }
}
}
+
+ ip++;
}
ralloc_free(cse_ctx);
- if (progress)
- invalidate_live_intervals();
-
return progress;
}
{
bool progress = false;
- cfg_t cfg(&instructions);
+ calculate_live_intervals();
- for (int b = 0; b < cfg.num_blocks; b++) {
- bblock_t *block = cfg.blocks[b];
- exec_list aeb;
-
- progress = opt_cse_local(block, &aeb) || progress;
+ foreach_block (block, cfg) {
+ progress = opt_cse_local(block) || progress;
}
+ if (progress)
+ invalidate_live_intervals();
+
return progress;
}