*/
#include "brw_vec4.h"
-#include "glsl/ir_print_visitor.h"
extern "C" {
#include "brw_eu.h"
+#include "main/macros.h"
+#include "program/prog_print.h"
+#include "program/prog_parameter.h"
};
-using namespace brw;
-
namespace brw {
-int
-vec4_visitor::setup_attributes(int payload_reg)
-{
- int nr_attributes;
- int attribute_map[VERT_ATTRIB_MAX];
-
- nr_attributes = 0;
- for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
- attribute_map[i] = payload_reg + nr_attributes;
- nr_attributes++;
- }
- }
-
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
- /* We have to support ATTR as a destination for GL_FIXED fixup. */
- if (inst->dst.file == ATTR) {
- int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
-
- struct brw_reg reg = brw_vec8_grf(grf, 0);
- reg.dw1.bits.writemask = inst->dst.writemask;
-
- inst->dst.file = HW_REG;
- inst->dst.fixed_hw_reg = reg;
- }
-
- for (int i = 0; i < 3; i++) {
- if (inst->src[i].file != ATTR)
- continue;
-
- int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
-
- struct brw_reg reg = brw_vec8_grf(grf, 0);
- reg.dw1.bits.swizzle = inst->src[i].swizzle;
- if (inst->src[i].abs)
- reg = brw_abs(reg);
- if (inst->src[i].negate)
- reg = negate(reg);
-
- inst->src[i].file = HW_REG;
- inst->src[i].fixed_hw_reg = reg;
- }
- }
-
- /* The BSpec says we always have to read at least one thing from
- * the VF, and it appears that the hardware wedges otherwise.
- */
- if (nr_attributes == 0)
- nr_attributes = 1;
-
- prog_data->urb_read_length = (nr_attributes + 1) / 2;
-
- return payload_reg + nr_attributes;
-}
-
-int
-vec4_visitor::setup_uniforms(int reg)
-{
- /* The pre-gen6 VS requires that some push constants get loaded no
- * matter what, or the GPU would hang.
- */
- if (intel->gen < 6 && this->uniforms == 0) {
- this->uniform_vector_size[this->uniforms] = 1;
-
- for (unsigned int i = 0; i < 4; i++) {
- unsigned int slot = this->uniforms * 4 + i;
- static float zero = 0.0;
- c->prog_data.param[slot] = &zero;
- }
-
- this->uniforms++;
- reg++;
- } else {
- reg += ALIGN(uniforms, 2) / 2;
- }
-
- c->prog_data.nr_params = this->uniforms * 4;
-
- c->prog_data.curb_read_length = reg - 1;
- c->prog_data.uses_new_param_layout = true;
-
- return reg;
-}
-
-void
-vec4_visitor::setup_payload(void)
-{
- int reg = 0;
-
- /* The payload always contains important data in g0, which contains
- * the URB handles that are passed on to the URB write at the end
- * of the thread. So, we always start push constants at g1.
- */
- reg++;
-
- reg = setup_uniforms(reg);
-
- reg = setup_attributes(reg);
-
- this->first_non_payload_grf = reg;
-}
-
struct brw_reg
vec4_instruction::get_dst(void)
{
}
struct brw_reg
-vec4_instruction::get_src(int i)
+vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
{
struct brw_reg brw_reg;
break;
case UNIFORM:
- brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
+ brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
+ (src[i].reg + src[i].reg_offset) / 2,
((src[i].reg + src[i].reg_offset) % 2) * 4),
0, 4, 1);
brw_reg = retype(brw_reg, src[i].type);
return brw_reg;
}
+vec4_generator::vec4_generator(struct brw_context *brw,
+ struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
+ struct brw_vec4_prog_data *prog_data,
+ void *mem_ctx,
+ bool debug_flag)
+ : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
+ mem_ctx(mem_ctx), debug_flag(debug_flag)
+{
+ shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
+
+ p = rzalloc(mem_ctx, struct brw_compile);
+ brw_init_compile(brw, p, mem_ctx);
+}
+
+vec4_generator::~vec4_generator()
+{
+}
+
+void
+vec4_generator::mark_surface_used(unsigned surf_index)
+{
+ assert(surf_index < BRW_MAX_VS_SURFACES);
+
+ prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
+ surf_index + 1);
+}
+
void
-vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src)
+vec4_generator::generate_math1_gen4(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src)
{
brw_math(p,
dst,
brw_math_function(inst->opcode),
- BRW_MATH_SATURATE_NONE,
inst->base_mrf,
src,
BRW_MATH_DATA_VECTOR,
/* Source swizzles are ignored. */
assert(!src.abs);
assert(!src.negate);
- assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
+ assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
}
void
-vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src)
+vec4_generator::generate_math1_gen6(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src)
{
/* Can't do writemask because math can't be align16. */
assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
brw_math(p,
dst,
brw_math_function(inst->opcode),
- BRW_MATH_SATURATE_NONE,
inst->base_mrf,
src,
BRW_MATH_DATA_SCALAR,
}
void
-vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1)
+vec4_generator::generate_math2_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
+{
+ brw_math2(p,
+ dst,
+ brw_math_function(inst->opcode),
+ src0, src1);
+}
+
+void
+vec4_generator::generate_math2_gen6(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
/* Can't do writemask because math can't be align16. */
assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
}
void
-vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src0,
- struct brw_reg src1)
+vec4_generator::generate_math2_gen4(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
- brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
+ /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
+ * "Message Payload":
+ *
+ * "Operand0[7]. For the INT DIV functions, this operand is the
+ * denominator."
+ * ...
+ * "Operand1[7]. For the INT DIV functions, this operand is the
+ * numerator."
+ */
+ bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
+ struct brw_reg &op0 = is_int_div ? src1 : src0;
+ struct brw_reg &op1 = is_int_div ? src0 : src1;
+
+ brw_push_insn_state(p);
+ brw_set_saturate(p, false);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
+ brw_pop_insn_state(p);
brw_math(p,
dst,
brw_math_function(inst->opcode),
- BRW_MATH_SATURATE_NONE,
inst->base_mrf,
- src0,
+ op0,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
}
void
-vec4_visitor::generate_urb_write(vec4_instruction *inst)
+vec4_generator::generate_tex(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+ int msg_type = -1;
+
+ if (brw->gen >= 5) {
+ switch (inst->opcode) {
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXL:
+ if (inst->shadow_compare) {
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+ } else {
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+ }
+ break;
+ case SHADER_OPCODE_TXD:
+ if (inst->shadow_compare) {
+ /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
+ assert(brw->is_haswell);
+ msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
+ } else {
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
+ }
+ break;
+ case SHADER_OPCODE_TXF:
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+ break;
+ case SHADER_OPCODE_TXF_MS:
+ if (brw->gen >= 7)
+ msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
+ else
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+ break;
+ case SHADER_OPCODE_TXS:
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+ break;
+ default:
+ assert(!"should not get here: invalid VS texture opcode");
+ break;
+ }
+ } else {
+ switch (inst->opcode) {
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXL:
+ if (inst->shadow_compare) {
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
+ assert(inst->mlen == 3);
+ } else {
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
+ assert(inst->mlen == 2);
+ }
+ break;
+ case SHADER_OPCODE_TXD:
+ /* There is no sample_d_c message; comparisons are done manually. */
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
+ assert(inst->mlen == 4);
+ break;
+ case SHADER_OPCODE_TXF:
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
+ assert(inst->mlen == 2);
+ break;
+ case SHADER_OPCODE_TXS:
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
+ assert(inst->mlen == 2);
+ break;
+ default:
+ assert(!"should not get here: invalid VS texture opcode");
+ break;
+ }
+ }
+
+ assert(msg_type != -1);
+
+ /* Load the message header if present. If there's a texture offset, we need
+ * to set it up explicitly and load the offset bitfield. Otherwise, we can
+ * use an implied move from g0 to the first message register.
+ */
+ if (inst->texture_offset) {
+ /* Explicitly set up the message header by copying g0 to the MRF. */
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
+ retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+
+ /* Then set the offset bits in DWord 2. */
+ brw_set_access_mode(p, BRW_ALIGN_1);
+ brw_MOV(p,
+ retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
+ BRW_REGISTER_TYPE_UD),
+ brw_imm_uw(inst->texture_offset));
+ brw_pop_insn_state(p);
+ } else if (inst->header_present) {
+ /* Set up an implied move from g0 to the MRF. */
+ src = brw_vec8_grf(0, 0);
+ }
+
+ uint32_t return_format;
+
+ switch (dst.type) {
+ case BRW_REGISTER_TYPE_D:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
+ break;
+ default:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
+ break;
+ }
+
+ brw_SAMPLE(p,
+ dst,
+ inst->base_mrf,
+ src,
+ SURF_INDEX_VS_TEXTURE(inst->sampler),
+ inst->sampler,
+ msg_type,
+ 1, /* response length */
+ inst->mlen,
+ inst->header_present,
+ BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+ return_format);
+
+ mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
+}
+
+void
+vec4_generator::generate_urb_write(vec4_instruction *inst)
{
brw_urb_WRITE(p,
brw_null_reg(), /* dest */
}
void
-vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
- struct brw_reg index)
+vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
+ struct brw_reg index)
{
int second_vertex_offset;
- if (intel->gen >= 6)
+ if (brw->gen >= 6)
second_vertex_offset = 1;
else
second_vertex_offset = 16;
brw_MOV(p, m1_0, index_0);
- brw_set_predicate_inverse(p, true);
if (index.file == BRW_IMMEDIATE_VALUE) {
index_4.dw1.ud += second_vertex_offset;
brw_MOV(p, m1_4, index_4);
}
void
-vec4_visitor::generate_scratch_read(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg index)
+vec4_generator::generate_unpack_flags(vec4_instruction *inst,
+ struct brw_reg dst)
+{
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_set_access_mode(p, BRW_ALIGN_1);
+
+ struct brw_reg flags = brw_flag_reg(0, 0);
+ struct brw_reg dst_0 = suboffset(vec1(dst), 0);
+ struct brw_reg dst_4 = suboffset(vec1(dst), 4);
+
+ brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
+ brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
+ brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
+
+ brw_pop_insn_state(p);
+}
+
+void
+vec4_generator::generate_scratch_read(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg index)
{
struct brw_reg header = brw_vec8_grf(0, 0);
uint32_t msg_type;
- if (intel->gen >= 6)
+ if (brw->gen >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
- else if (intel->gen == 5 || intel->is_g4x)
+ else if (brw->gen == 5 || brw->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
- if (intel->gen < 6)
+ if (brw->gen < 6)
send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_read_message(p, send,
255, /* binding table index: stateless access */
msg_type,
BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
2, /* mlen */
+ true, /* header_present */
1 /* rlen */);
}
void
-vec4_visitor::generate_scratch_write(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg src,
- struct brw_reg index)
+vec4_generator::generate_scratch_write(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src,
+ struct brw_reg index)
{
struct brw_reg header = brw_vec8_grf(0, 0);
bool write_commit;
uint32_t msg_type;
- if (intel->gen >= 6)
+ if (brw->gen >= 7)
+ msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
+ else if (brw->gen == 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
* guaranteed and write commits only matter for inter-thread
* synchronization.
*/
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
write_commit = false;
} else {
/* The visitor set up our destination register to be g0. This
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
- if (intel->gen < 6)
+ if (brw->gen < 6)
send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_write_message(p, send,
255, /* binding table index: stateless access */
msg_type,
3, /* mlen */
true, /* header present */
- false, /* pixel scoreboard */
+ false, /* not a render target write */
write_commit, /* rlen */
false, /* eot */
write_commit);
}
void
-vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
- struct brw_reg dst,
- struct brw_reg index)
+vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg index,
+ struct brw_reg offset)
{
+ assert(brw->gen <= 7);
+ assert(index.file == BRW_IMMEDIATE_VALUE &&
+ index.type == BRW_REGISTER_TYPE_UD);
+ uint32_t surf_index = index.dw1.ud;
+
struct brw_reg header = brw_vec8_grf(0, 0);
gen6_resolve_implied_move(p, &header, inst->base_mrf);
brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
- index);
+ offset);
uint32_t msg_type;
- if (intel->gen >= 6)
+ if (brw->gen >= 6)
msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
- else if (intel->gen == 5 || intel->is_g4x)
+ else if (brw->gen == 5 || brw->is_g4x)
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
else
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
- if (intel->gen < 6)
+ if (brw->gen < 6)
send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_read_message(p, send,
- SURF_INDEX_VERT_CONST_BUFFER,
+ surf_index,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
msg_type,
BRW_DATAPORT_READ_TARGET_DATA_CACHE,
2, /* mlen */
+ true, /* header_present */
1 /* rlen */);
+
+ mark_surface_used(surf_index);
+}
+
+void
+vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg surf_index,
+ struct brw_reg offset)
+{
+ assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
+ surf_index.type == BRW_REGISTER_TYPE_UD);
+
+ brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
+ brw_set_dest(p, insn, dst);
+ brw_set_src0(p, insn, offset);
+ brw_set_sampler_message(p, insn,
+ surf_index.dw1.ud,
+ 0, /* LD message ignores sampler unit */
+ GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+ 1, /* rlen */
+ 1, /* mlen */
+ false, /* no header */
+ BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+ 0);
+
+ mark_surface_used(surf_index.dw1.ud);
}
+/**
+ * Generate assembly for a Vec4 IR instruction.
+ *
+ * \param instruction The Vec4 IR instruction to generate code for.
+ * \param dst The destination register.
+ * \param src An array of up to three source registers.
+ */
void
-vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
- struct brw_reg dst,
- struct brw_reg *src)
+vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
+ struct brw_reg dst,
+ struct brw_reg *src)
{
- vec4_instruction *inst = (vec4_instruction *)instruction;
+ vec4_instruction *inst = (vec4_instruction *) instruction;
switch (inst->opcode) {
+ case BRW_OPCODE_MOV:
+ brw_MOV(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_ADD:
+ brw_ADD(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_MUL:
+ brw_MUL(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_MACH:
+ brw_set_acc_write_control(p, 1);
+ brw_MACH(p, dst, src[0], src[1]);
+ brw_set_acc_write_control(p, 0);
+ break;
+
+ case BRW_OPCODE_MAD:
+ brw_MAD(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_FRC:
+ brw_FRC(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_RNDD:
+ brw_RNDD(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_RNDE:
+ brw_RNDE(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_RNDZ:
+ brw_RNDZ(p, dst, src[0]);
+ break;
+
+ case BRW_OPCODE_AND:
+ brw_AND(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_OR:
+ brw_OR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_XOR:
+ brw_XOR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_NOT:
+ brw_NOT(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_ASR:
+ brw_ASR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_SHR:
+ brw_SHR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_SHL:
+ brw_SHL(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_CMP:
+ brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
+ break;
+ case BRW_OPCODE_SEL:
+ brw_SEL(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_DPH:
+ brw_DPH(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_DP4:
+ brw_DP4(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_DP3:
+ brw_DP3(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_DP2:
+ brw_DP2(p, dst, src[0], src[1]);
+ break;
+
+ case BRW_OPCODE_F32TO16:
+ brw_F32TO16(p, dst, src[0]);
+ break;
+
+ case BRW_OPCODE_F16TO32:
+ brw_F16TO32(p, dst, src[0]);
+ break;
+
+ case BRW_OPCODE_LRP:
+ brw_LRP(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and dst. */
+ brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
+ retype(src[0], BRW_REGISTER_TYPE_UD));
+ break;
+ case BRW_OPCODE_FBH:
+ /* FBH only supports UD type for dst. */
+ brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_FBL:
+ /* FBL only supports UD type for dst. */
+ brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_CBIT:
+ /* CBIT only supports UD type for dst. */
+ brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+
+ case BRW_OPCODE_BFE:
+ brw_BFE(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_BFI1:
+ brw_BFI1(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_BFI2:
+ brw_BFI2(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_IF:
+ if (inst->src[0].file != BAD_FILE) {
+ /* The instruction has an embedded compare (only allowed on gen6) */
+ assert(brw->gen == 6);
+ gen6_IF(p, inst->conditional_mod, src[0], src[1]);
+ } else {
+ struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
+ brw_inst->header.predicate_control = inst->predicate;
+ }
+ break;
+
+ case BRW_OPCODE_ELSE:
+ brw_ELSE(p);
+ break;
+ case BRW_OPCODE_ENDIF:
+ brw_ENDIF(p);
+ break;
+
+ case BRW_OPCODE_DO:
+ brw_DO(p, BRW_EXECUTE_8);
+ break;
+
+ case BRW_OPCODE_BREAK:
+ brw_BREAK(p);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ break;
+ case BRW_OPCODE_CONTINUE:
+ /* FINISHME: We need to write the loop instruction support still. */
+ if (brw->gen >= 6)
+ gen6_CONT(p);
+ else
+ brw_CONT(p);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ break;
+
+ case BRW_OPCODE_WHILE:
+ brw_WHILE(p);
+ break;
+
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
- if (intel->gen >= 6) {
+ if (brw->gen == 6) {
generate_math1_gen6(inst, dst, src[0]);
} else {
+ /* Also works for Gen7. */
generate_math1_gen4(inst, dst, src[0]);
}
break;
case SHADER_OPCODE_POW:
- if (intel->gen >= 6) {
+ case SHADER_OPCODE_INT_QUOTIENT:
+ case SHADER_OPCODE_INT_REMAINDER:
+ if (brw->gen >= 7) {
+ generate_math2_gen7(inst, dst, src[0], src[1]);
+ } else if (brw->gen == 6) {
generate_math2_gen6(inst, dst, src[0], src[1]);
} else {
generate_math2_gen4(inst, dst, src[0], src[1]);
}
break;
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXF_MS:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXS:
+ generate_tex(inst, dst, src[0]);
+ break;
+
case VS_OPCODE_URB_WRITE:
generate_urb_write(inst);
break;
break;
case VS_OPCODE_PULL_CONSTANT_LOAD:
- generate_pull_constant_load(inst, dst, src[0]);
+ generate_pull_constant_load(inst, dst, src[0], src[1]);
+ break;
+
+ case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
+ generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
+ break;
+
+ case SHADER_OPCODE_SHADER_TIME_ADD:
+ brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
+ mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
+ break;
+
+ case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
+ generate_unpack_flags(inst, dst);
break;
default:
- if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
- fail("unsupported opcode in `%s' in VS\n",
- brw_opcodes[inst->opcode].name);
+ if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
+ _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
+ opcode_descs[inst->opcode].name);
} else {
- fail("Unsupported opcode %d in VS", inst->opcode);
+ _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
}
+ abort();
}
}
-bool
-vec4_visitor::run()
-{
- if (c->key.nr_userclip && !c->key.uses_clip_distance)
- setup_uniform_clipplane_values();
-
- /* Generate VS IR for main(). (the visitor only descends into
- * functions called "main").
- */
- visit_instructions(shader->ir);
-
- emit_urb_writes();
-
- /* Before any optimization, push array accesses out to scratch
- * space where we need them to be. This pass may allocate new
- * virtual GRFs, so we want to do it early. It also makes sure
- * that we have reladdr computations available for CSE, since we'll
- * often do repeated subexpressions for those.
- */
- move_grf_array_access_to_scratch();
- move_uniform_array_access_to_pull_constants();
- pack_uniform_registers();
- move_push_constants_to_pull_constants();
-
- bool progress;
- do {
- progress = false;
- progress = dead_code_eliminate() || progress;
- progress = opt_copy_propagation() || progress;
- progress = opt_algebraic() || progress;
- progress = opt_compute_to_mrf() || progress;
- } while (progress);
-
-
- if (failed)
- return false;
-
- setup_payload();
- reg_allocate();
-
- if (failed)
- return false;
-
- brw_set_access_mode(p, BRW_ALIGN_16);
-
- generate_code();
-
- return !failed;
-}
-
void
-vec4_visitor::generate_code()
+vec4_generator::generate_code(exec_list *instructions)
{
- int last_native_inst = 0;
+ int last_native_insn_offset = 0;
const char *last_annotation_string = NULL;
- ir_instruction *last_annotation_ir = NULL;
+ const void *last_annotation_ir = NULL;
- int loop_stack_array_size = 16;
- int loop_stack_depth = 0;
- brw_instruction **loop_stack =
- rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
- int *if_depth_in_loop =
- rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
-
-
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
- printf("Native code for vertex shader %d:\n", prog->Name);
+ if (unlikely(debug_flag)) {
+ if (shader) {
+ printf("Native code for vertex shader %d:\n", shader_prog->Name);
+ } else {
+ printf("Native code for vertex program %d:\n", prog->Id);
+ }
}
- foreach_list(node, &this->instructions) {
+ foreach_list(node, instructions) {
vec4_instruction *inst = (vec4_instruction *)node;
struct brw_reg src[3], dst;
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
+ if (unlikely(debug_flag)) {
if (last_annotation_ir != inst->ir) {
last_annotation_ir = inst->ir;
if (last_annotation_ir) {
printf(" ");
- last_annotation_ir->print();
+ if (shader) {
+ ((ir_instruction *) last_annotation_ir)->print();
+ } else {
+ const prog_instruction *vpi;
+ vpi = (const prog_instruction *) inst->ir;
+ printf("%d: ", (int)(vpi - prog->Instructions));
+ _mesa_fprint_instruction_opt(stdout, vpi, 0,
+ PROG_PRINT_DEBUG, NULL);
+ }
printf("\n");
}
}
}
for (unsigned int i = 0; i < 3; i++) {
- src[i] = inst->get_src(i);
+ src[i] = inst->get_src(this->prog_data, i);
}
dst = inst->get_dst();
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
+ brw_set_mask_control(p, inst->force_writemask_all);
- switch (inst->opcode) {
- case BRW_OPCODE_MOV:
- brw_MOV(p, dst, src[0]);
- break;
- case BRW_OPCODE_ADD:
- brw_ADD(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_MUL:
- brw_MUL(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_MACH:
- brw_set_acc_write_control(p, 1);
- brw_MACH(p, dst, src[0], src[1]);
- brw_set_acc_write_control(p, 0);
- break;
-
- case BRW_OPCODE_FRC:
- brw_FRC(p, dst, src[0]);
- break;
- case BRW_OPCODE_RNDD:
- brw_RNDD(p, dst, src[0]);
- break;
- case BRW_OPCODE_RNDE:
- brw_RNDE(p, dst, src[0]);
- break;
- case BRW_OPCODE_RNDZ:
- brw_RNDZ(p, dst, src[0]);
- break;
-
- case BRW_OPCODE_AND:
- brw_AND(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_OR:
- brw_OR(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_XOR:
- brw_XOR(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_NOT:
- brw_NOT(p, dst, src[0]);
- break;
- case BRW_OPCODE_ASR:
- brw_ASR(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_SHR:
- brw_SHR(p, dst, src[0], src[1]);
- break;
- case BRW_OPCODE_SHL:
- brw_SHL(p, dst, src[0], src[1]);
- break;
-
- case BRW_OPCODE_CMP:
- brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
- break;
- case BRW_OPCODE_SEL:
- brw_SEL(p, dst, src[0], src[1]);
- break;
+ unsigned pre_emit_nr_insn = p->nr_insn;
- case BRW_OPCODE_DP4:
- brw_DP4(p, dst, src[0], src[1]);
- break;
+ generate_vec4_instruction(inst, dst, src);
- case BRW_OPCODE_DP3:
- brw_DP3(p, dst, src[0], src[1]);
- break;
+ if (inst->no_dd_clear || inst->no_dd_check) {
+ assert(p->nr_insn == pre_emit_nr_insn + 1 ||
+ !"no_dd_check or no_dd_clear set for IR emitting more "
+ "than 1 instruction");
- case BRW_OPCODE_DP2:
- brw_DP2(p, dst, src[0], src[1]);
- break;
+ struct brw_instruction *last = &p->store[pre_emit_nr_insn];
- case BRW_OPCODE_IF:
- if (inst->src[0].file != BAD_FILE) {
- /* The instruction has an embedded compare (only allowed on gen6) */
- assert(intel->gen == 6);
- gen6_IF(p, inst->conditional_mod, src[0], src[1]);
- } else {
- struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
- brw_inst->header.predicate_control = inst->predicate;
- }
- if_depth_in_loop[loop_stack_depth]++;
- break;
-
- case BRW_OPCODE_ELSE:
- brw_ELSE(p);
- break;
- case BRW_OPCODE_ENDIF:
- brw_ENDIF(p);
- if_depth_in_loop[loop_stack_depth]--;
- break;
-
- case BRW_OPCODE_DO:
- loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
- if (loop_stack_array_size <= loop_stack_depth) {
- loop_stack_array_size *= 2;
- loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
- loop_stack_array_size);
- if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
- loop_stack_array_size);
- }
- if_depth_in_loop[loop_stack_depth] = 0;
- break;
-
- case BRW_OPCODE_BREAK:
- brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
- break;
- case BRW_OPCODE_CONTINUE:
- /* FINISHME: We need to write the loop instruction support still. */
- if (intel->gen >= 6)
- gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
- else
- brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
- break;
-
- case BRW_OPCODE_WHILE: {
- struct brw_instruction *inst0, *inst1;
- GLuint br = 1;
-
- if (intel->gen >= 5)
- br = 2;
-
- assert(loop_stack_depth > 0);
- loop_stack_depth--;
- inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
- if (intel->gen < 6) {
- /* patch all the BREAK/CONT instructions from last BGNLOOP */
- while (inst0 > loop_stack[loop_stack_depth]) {
- inst0--;
- if (inst0->header.opcode == BRW_OPCODE_BREAK &&
- inst0->bits3.if_else.jump_count == 0) {
- inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
- }
- else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
- inst0->bits3.if_else.jump_count == 0) {
- inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
- }
- }
- }
+ if (inst->no_dd_clear)
+ last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
+ if (inst->no_dd_check)
+ last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
}
- break;
- default:
- generate_vs_instruction(inst, dst, src);
- break;
- }
-
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
- for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
- if (0) {
- printf("0x%08x 0x%08x 0x%08x 0x%08x ",
- ((uint32_t *)&p->store[i])[3],
- ((uint32_t *)&p->store[i])[2],
- ((uint32_t *)&p->store[i])[1],
- ((uint32_t *)&p->store[i])[0]);
- }
- brw_disasm(stdout, &p->store[i], intel->gen);
- }
+ if (unlikely(debug_flag)) {
+ brw_dump_compile(p, stdout,
+ last_native_insn_offset, p->next_insn_offset);
}
- last_native_inst = p->nr_insn;
+ last_native_insn_offset = p->next_insn_offset;
}
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
+ if (unlikely(debug_flag)) {
printf("\n");
}
- ralloc_free(loop_stack);
- ralloc_free(if_depth_in_loop);
-
brw_set_uip_jip(p);
/* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
* which is often something we want to debug. So this is here in
* case you're doing that.
*/
- if (0) {
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
- for (unsigned int i = 0; i < p->nr_insn; i++) {
- printf("0x%08x 0x%08x 0x%08x 0x%08x ",
- ((uint32_t *)&p->store[i])[3],
- ((uint32_t *)&p->store[i])[2],
- ((uint32_t *)&p->store[i])[1],
- ((uint32_t *)&p->store[i])[0]);
- brw_disasm(stdout, &p->store[i], intel->gen);
- }
- }
+ if (0 && unlikely(debug_flag)) {
+ brw_dump_compile(p, stdout, 0, p->next_insn_offset);
}
}
-extern "C" {
-
-bool
-brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
+const unsigned *
+vec4_generator::generate_assembly(exec_list *instructions,
+ unsigned *assembly_size)
{
- if (!prog)
- return false;
-
- struct brw_shader *shader =
- (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
- if (!shader)
- return false;
-
- if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
- printf("GLSL IR for native vertex shader %d:\n", prog->Name);
- _mesa_print_ir(shader->ir, NULL);
- printf("\n\n");
- }
-
- vec4_visitor v(c, prog, shader);
- if (!v.run()) {
- prog->LinkStatus = GL_FALSE;
- ralloc_strcat(&prog->InfoLog, v.fail_msg);
- return false;
- }
-
- return true;
+ brw_set_access_mode(p, BRW_ALIGN_16);
+ generate_code(instructions);
+ return brw_get_program(p, assembly_size);
}
-} /* extern "C" */
-
} /* namespace brw */
projects / mesa.git / blobdiff