i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 6ebc318a13d11db1fabb893276ee8557e0300037..53b4bf2b30779704a69f6d48adbc164f5812668d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -66,7 +66,7 @@ vec4_instruction::get_dst(void)
 }
 
 struct brw_reg
-vec4_instruction::get_src(int i)
+vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
 {
    struct brw_reg brw_reg;
 
@@ -100,7 +100,8 @@ vec4_instruction::get_src(int i)
       break;
 
    case UNIFORM:
-      brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
+      brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
+                                    (src[i].reg + src[i].reg_offset) / 2,
                                    ((src[i].reg + src[i].reg_offset) % 2) * 4),
                       0, 4, 1);
       brw_reg = retype(brw_reg, src[i].type);
@@ -135,10 +136,11 @@ vec4_instruction::get_src(int i)
 vec4_generator::vec4_generator(struct brw_context *brw,
                                struct gl_shader_program *shader_prog,
                                struct gl_program *prog,
+                               struct brw_vec4_prog_data *prog_data,
                                void *mem_ctx,
                                bool debug_flag)
-   : brw(brw), shader_prog(shader_prog), prog(prog), mem_ctx(mem_ctx),
-     debug_flag(debug_flag)
+   : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
+     mem_ctx(mem_ctx), debug_flag(debug_flag)
 {
    shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
 
@@ -150,6 +152,15 @@ vec4_generator::~vec4_generator()
 {
 }
 
+void
+vec4_generator::mark_surface_used(unsigned surf_index)
+{
+   assert(surf_index < BRW_MAX_VS_SURFACES);
+
+   prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
+                                        surf_index + 1);
+}
+
 void
 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
                                     struct brw_reg dst,
@@ -383,6 +394,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
              inst->header_present,
              BRW_SAMPLER_SIMD_MODE_SIMD4X2,
              return_format);
+
+   mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
 }
 
 void
@@ -613,6 +626,8 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
                           2, /* mlen */
                            true, /* header_present */
                           1 /* rlen */);
+
+   mark_surface_used(surf_index);
 }
 
 void
@@ -636,6 +651,8 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
                            false, /* no header */
                            BRW_SAMPLER_SIMD_MODE_SIMD4X2,
                            0);
+
+   mark_surface_used(surf_index.dw1.ud);
 }
 
 /**
@@ -868,6 +885,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 
    case SHADER_OPCODE_SHADER_TIME_ADD:
       brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
+      mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
       break;
 
    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
@@ -929,7 +947,7 @@ vec4_generator::generate_code(exec_list *instructions)
       }
 
       for (unsigned int i = 0; i < 3; i++) {
-        src[i] = inst->get_src(i);
+        src[i] = inst->get_src(this->prog_data, i);
       }
       dst = inst->get_dst();