i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index f15759ff0b38e7d742d848a7c32ccbcd6b7cca32..53b4bf2b30779704a69f6d48adbc164f5812668d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -66,7 +66,7 @@ vec4_instruction::get_dst(void)
 }
 
 struct brw_reg
-vec4_instruction::get_src(int i)
+vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
 {
    struct brw_reg brw_reg;
 
@@ -100,7 +100,8 @@ vec4_instruction::get_src(int i)
       break;
 
    case UNIFORM:
-      brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
+      brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
+                                    (src[i].reg + src[i].reg_offset) / 2,
                                    ((src[i].reg + src[i].reg_offset) % 2) * 4),
                       0, 4, 1);
       brw_reg = retype(brw_reg, src[i].type);
@@ -135,13 +136,12 @@ vec4_instruction::get_src(int i)
 vec4_generator::vec4_generator(struct brw_context *brw,
                                struct gl_shader_program *shader_prog,
                                struct gl_program *prog,
+                               struct brw_vec4_prog_data *prog_data,
                                void *mem_ctx,
                                bool debug_flag)
-   : brw(brw), shader_prog(shader_prog), prog(prog), mem_ctx(mem_ctx),
-     debug_flag(debug_flag)
+   : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
+     mem_ctx(mem_ctx), debug_flag(debug_flag)
 {
-   intel = &brw->intel;
-
    shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
 
    p = rzalloc(mem_ctx, struct brw_compile);
@@ -152,6 +152,15 @@ vec4_generator::~vec4_generator()
 {
 }
 
+void
+vec4_generator::mark_surface_used(unsigned surf_index)
+{
+   assert(surf_index < BRW_MAX_VS_SURFACES);
+
+   prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
+                                        surf_index + 1);
+}
+
 void
 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
                                     struct brw_reg dst,
@@ -268,7 +277,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 {
    int msg_type = -1;
 
-   if (intel->gen >= 5) {
+   if (brw->gen >= 5) {
       switch (inst->opcode) {
       case SHADER_OPCODE_TEX:
       case SHADER_OPCODE_TXL:
@@ -281,7 +290,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TXD:
          if (inst->shadow_compare) {
             /* Gen7.5+.  Otherwise, lowered by brw_lower_texture_gradients(). */
-            assert(intel->is_haswell);
+            assert(brw->is_haswell);
             msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
          } else {
             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -291,7 +300,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
         break;
       case SHADER_OPCODE_TXF_MS:
-         if (intel->gen >= 7)
+         if (brw->gen >= 7)
             msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
          else
             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
@@ -385,6 +394,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
              inst->header_present,
              BRW_SAMPLER_SIMD_MODE_SIMD4X2,
              return_format);
+
+   mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
 }
 
 void
@@ -410,7 +421,7 @@ vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
 {
    int second_vertex_offset;
 
-   if (intel->gen >= 6)
+   if (brw->gen >= 6)
       second_vertex_offset = 1;
    else
       second_vertex_offset = 16;
@@ -441,6 +452,25 @@ vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
    brw_pop_insn_state(p);
 }
 
+void
+vec4_generator::generate_unpack_flags(vec4_instruction *inst,
+                                      struct brw_reg dst)
+{
+   brw_push_insn_state(p);
+   brw_set_mask_control(p, BRW_MASK_DISABLE);
+   brw_set_access_mode(p, BRW_ALIGN_1);
+
+   struct brw_reg flags = brw_flag_reg(0, 0);
+   struct brw_reg dst_0 = suboffset(vec1(dst), 0);
+   struct brw_reg dst_4 = suboffset(vec1(dst), 4);
+
+   brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
+   brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
+   brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
+
+   brw_pop_insn_state(p);
+}
+
 void
 vec4_generator::generate_scratch_read(vec4_instruction *inst,
                                       struct brw_reg dst,
@@ -455,9 +485,9 @@ vec4_generator::generate_scratch_read(vec4_instruction *inst,
 
    uint32_t msg_type;
 
-   if (intel->gen >= 6)
+   if (brw->gen >= 6)
       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
-   else if (intel->gen == 5 || intel->is_g4x)
+   else if (brw->gen == 5 || brw->is_g4x)
       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
    else
       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@@ -468,7 +498,7 @@ vec4_generator::generate_scratch_read(vec4_instruction *inst,
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
    brw_set_src0(p, send, header);
-   if (intel->gen < 6)
+   if (brw->gen < 6)
       send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_read_message(p, send,
                           255, /* binding table index: stateless access */
@@ -505,9 +535,9 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
 
    uint32_t msg_type;
 
-   if (intel->gen >= 7)
+   if (brw->gen >= 7)
       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
-   else if (intel->gen == 6)
+   else if (brw->gen == 6)
       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
    else
       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
@@ -519,7 +549,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
     * guaranteed and write commits only matter for inter-thread
     * synchronization.
     */
-   if (intel->gen >= 6) {
+   if (brw->gen >= 6) {
       write_commit = false;
    } else {
       /* The visitor set up our destination register to be g0.  This
@@ -539,7 +569,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
    brw_set_src0(p, send, header);
-   if (intel->gen < 6)
+   if (brw->gen < 6)
       send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_write_message(p, send,
                            255, /* binding table index: stateless access */
@@ -559,7 +589,7 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
                                             struct brw_reg index,
                                             struct brw_reg offset)
 {
-   assert(intel->gen <= 7);
+   assert(brw->gen <= 7);
    assert(index.file == BRW_IMMEDIATE_VALUE &&
          index.type == BRW_REGISTER_TYPE_UD);
    uint32_t surf_index = index.dw1.ud;
@@ -573,9 +603,9 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
 
    uint32_t msg_type;
 
-   if (intel->gen >= 6)
+   if (brw->gen >= 6)
       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
-   else if (intel->gen == 5 || intel->is_g4x)
+   else if (brw->gen == 5 || brw->is_g4x)
       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
    else
       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
@@ -586,7 +616,7 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
    brw_set_src0(p, send, header);
-   if (intel->gen < 6)
+   if (brw->gen < 6)
       send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_read_message(p, send,
                           surf_index,
@@ -596,6 +626,8 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
                           2, /* mlen */
                            true, /* header_present */
                           1 /* rlen */);
+
+   mark_surface_used(surf_index);
 }
 
 void
@@ -619,6 +651,8 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
                            false, /* no header */
                            BRW_SAMPLER_SIMD_MODE_SIMD4X2,
                            0);
+
+   mark_surface_used(surf_index.dw1.ud);
 }
 
 /**
@@ -757,7 +791,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case BRW_OPCODE_IF:
       if (inst->src[0].file != BAD_FILE) {
          /* The instruction has an embedded compare (only allowed on gen6) */
-         assert(intel->gen == 6);
+         assert(brw->gen == 6);
          gen6_IF(p, inst->conditional_mod, src[0], src[1]);
       } else {
          struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
@@ -782,7 +816,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
    case BRW_OPCODE_CONTINUE:
       /* FINISHME: We need to write the loop instruction support still. */
-      if (intel->gen >= 6)
+      if (brw->gen >= 6)
          gen6_CONT(p);
       else
          brw_CONT(p);
@@ -800,7 +834,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_LOG2:
    case SHADER_OPCODE_SIN:
    case SHADER_OPCODE_COS:
-      if (intel->gen == 6) {
+      if (brw->gen == 6) {
         generate_math1_gen6(inst, dst, src[0]);
       } else {
         /* Also works for Gen7. */
@@ -811,9 +845,9 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_POW:
    case SHADER_OPCODE_INT_QUOTIENT:
    case SHADER_OPCODE_INT_REMAINDER:
-      if (intel->gen >= 7) {
+      if (brw->gen >= 7) {
         generate_math2_gen7(inst, dst, src[0], src[1]);
-      } else if (intel->gen == 6) {
+      } else if (brw->gen == 6) {
         generate_math2_gen6(inst, dst, src[0], src[1]);
       } else {
         generate_math2_gen4(inst, dst, src[0], src[1]);
@@ -851,6 +885,11 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 
    case SHADER_OPCODE_SHADER_TIME_ADD:
       brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
+      mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
+      break;
+
+   case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
+      generate_unpack_flags(inst, dst);
       break;
 
    default:
@@ -908,7 +947,7 @@ vec4_generator::generate_code(exec_list *instructions)
       }
 
       for (unsigned int i = 0; i < 3; i++) {
-        src[i] = inst->get_src(i);
+        src[i] = inst->get_src(this->prog_data, i);
       }
       dst = inst->get_dst();