vec4_visitor::setup_attributes(int payload_reg)
{
int nr_attributes;
- int attribute_map[VERT_ATTRIB_MAX];
+ int attribute_map[VERT_ATTRIB_MAX + 1];
nr_attributes = 0;
for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
}
}
+ /* VertexID is stored by the VF as the last vertex element, but we
+ * don't represent it with a flag in inputs_read, so we call it
+ * VERT_ATTRIB_MAX.
+ */
+ if (prog_data->uses_vertexid) {
+ attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
+ nr_attributes++;
+ }
+
foreach_list(node, &this->instructions) {
vec4_instruction *inst = (vec4_instruction *)node;
struct brw_reg reg = brw_vec8_grf(grf, 0);
reg.dw1.bits.swizzle = inst->src[i].swizzle;
+ reg.type = inst->src[i].type;
if (inst->src[i].abs)
reg = brw_abs(reg);
if (inst->src[i].negate)
int
vec4_visitor::setup_uniforms(int reg)
{
- /* User clip planes from curbe:
- */
- if (c->key.nr_userclip) {
- if (intel->gen >= 6) {
- for (int i = 0; i < c->key.nr_userclip; i++) {
- c->userplane[i] = stride(brw_vec4_grf(reg + i / 2,
- (i % 2) * 4), 0, 4, 1);
- }
- reg += ALIGN(c->key.nr_userclip, 2) / 2;
- } else {
- for (int i = 0; i < c->key.nr_userclip; i++) {
- c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2,
- (i % 2) * 4), 0, 4, 1);
- }
- reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2;
- }
- }
-
/* The pre-gen6 VS requires that some push constants get loaded no
* matter what, or the GPU would hang.
*/
brw_reg.dw1.bits.writemask = dst.writemask;
break;
+ case MRF:
+ brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
+ brw_reg = retype(brw_reg, dst.type);
+ brw_reg.dw1.bits.writemask = dst.writemask;
+ break;
+
case HW_REG:
brw_reg = dst.fixed_hw_reg;
break;
BRW_MATH_SATURATE_NONE,
inst->base_mrf,
src,
- BRW_MATH_DATA_SCALAR,
+ BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
}
/* Source swizzles are ignored. */
assert(!src.abs);
assert(!src.negate);
- assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
+ assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
}
void
brw_set_access_mode(p, BRW_ALIGN_16);
}
+void
+vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src0,
+ struct brw_reg src1)
+{
+ brw_math2(p,
+ dst,
+ brw_math_function(inst->opcode),
+ src0, src1);
+}
+
void
vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1)
{
- brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
+ /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
+ * "Message Payload":
+ *
+ * "Operand0[7]. For the INT DIV functions, this operand is the
+ * denominator."
+ * ...
+ * "Operand1[7]. For the INT DIV functions, this operand is the
+ * numerator."
+ */
+ bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
+ struct brw_reg &op0 = is_int_div ? src1 : src0;
+ struct brw_reg &op1 = is_int_div ? src0 : src1;
+
+ brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
brw_math(p,
dst,
brw_math_function(inst->opcode),
BRW_MATH_SATURATE_NONE,
inst->base_mrf,
- src0,
+ op0,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
}
+void
+vec4_visitor::generate_tex(vec4_instruction *inst,
+ struct brw_reg dst,
+ struct brw_reg src)
+{
+ int msg_type = -1;
+
+ if (intel->gen >= 5) {
+ switch (inst->opcode) {
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXL:
+ if (inst->shadow_compare) {
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+ } else {
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+ }
+ break;
+ case SHADER_OPCODE_TXD:
+ /* There is no sample_d_c message; comparisons are done manually. */
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
+ break;
+ case SHADER_OPCODE_TXF:
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+ break;
+ case SHADER_OPCODE_TXS:
+ msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+ break;
+ default:
+ assert(!"should not get here: invalid VS texture opcode");
+ break;
+ }
+ } else {
+ switch (inst->opcode) {
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXL:
+ if (inst->shadow_compare) {
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
+ assert(inst->mlen == 3);
+ } else {
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
+ assert(inst->mlen == 2);
+ }
+ break;
+ case SHADER_OPCODE_TXD:
+ /* There is no sample_d_c message; comparisons are done manually. */
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
+ assert(inst->mlen == 4);
+ break;
+ case SHADER_OPCODE_TXF:
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
+ assert(inst->mlen == 2);
+ break;
+ case SHADER_OPCODE_TXS:
+ msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
+ assert(inst->mlen == 2);
+ break;
+ default:
+ assert(!"should not get here: invalid VS texture opcode");
+ break;
+ }
+ }
+
+ assert(msg_type != -1);
+
+ /* Load the message header if present. If there's a texture offset, we need
+ * to set it up explicitly and load the offset bitfield. Otherwise, we can
+ * use an implied move from g0 to the first message register.
+ */
+ if (inst->texture_offset) {
+ /* Explicitly set up the message header by copying g0 to the MRF. */
+ brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
+ retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+
+ /* Then set the offset bits in DWord 2. */
+ brw_set_access_mode(p, BRW_ALIGN_1);
+ brw_MOV(p,
+ retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
+ BRW_REGISTER_TYPE_UD),
+ brw_imm_uw(inst->texture_offset));
+ brw_set_access_mode(p, BRW_ALIGN_16);
+ } else if (inst->header_present) {
+ /* Set up an implied move from g0 to the MRF. */
+ src = brw_vec8_grf(0, 0);
+ }
+
+ uint32_t return_format;
+
+ switch (dst.type) {
+ case BRW_REGISTER_TYPE_D:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
+ break;
+ default:
+ return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
+ break;
+ }
+
+ brw_SAMPLE(p,
+ dst,
+ inst->base_mrf,
+ src,
+ SURF_INDEX_TEXTURE(inst->sampler),
+ inst->sampler,
+ WRITEMASK_XYZW,
+ msg_type,
+ 1, /* response length */
+ inst->mlen,
+ inst->header_present,
+ BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+ return_format);
+}
+
void
vec4_visitor::generate_urb_write(vec4_instruction *inst)
{
brw_set_predicate_inverse(p, true);
if (index.file == BRW_IMMEDIATE_VALUE) {
- index_4.dw1.ud++;
+ index_4.dw1.ud += second_vertex_offset;
brw_MOV(p, m1_4, index_4);
} else {
brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
struct brw_reg dst,
struct brw_reg index)
{
- if (intel->gen >= 6) {
- brw_push_insn_state(p);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
- brw_MOV(p,
- retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
- retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
- brw_pop_insn_state(p);
- }
+ struct brw_reg header = brw_vec8_grf(0, 0);
+
+ gen6_resolve_implied_move(p, &header, inst->base_mrf);
generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
index);
*/
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
- brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
+ brw_set_src0(p, send, header);
+ if (intel->gen < 6)
+ send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_read_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
struct brw_reg src,
struct brw_reg index)
{
+ struct brw_reg header = brw_vec8_grf(0, 0);
+ bool write_commit;
+
/* If the instruction is predicated, we'll predicate the send, not
* the header setup.
*/
brw_set_predicate_control(p, false);
- if (intel->gen >= 6) {
- brw_push_insn_state(p);
- brw_set_mask_control(p, BRW_MASK_DISABLE);
- brw_MOV(p,
- retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
- retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
- brw_pop_insn_state(p);
- }
+ gen6_resolve_implied_move(p, &header, inst->base_mrf);
generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
index);
uint32_t msg_type;
- if (intel->gen >= 6)
+ if (intel->gen >= 7)
+ msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
+ else if (intel->gen == 6)
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
brw_set_predicate_control(p, inst->predicate);
+ /* Pre-gen6, we have to specify write commits to ensure ordering
+ * between reads and writes within a thread. Afterwards, that's
+ * guaranteed and write commits only matter for inter-thread
+ * synchronization.
+ */
+ if (intel->gen >= 6) {
+ write_commit = false;
+ } else {
+ /* The visitor set up our destination register to be g0. This
+ * means that when the next read comes along, we will end up
+ * reading from g0 and causing a block on the write commit. For
+ * write-after-read, we are relying on the value of the previous
+ * read being used (and thus blocking on completion) before our
+ * write is executed. This means we have to be careful in
+ * instruction scheduling to not violate this assumption.
+ */
+ write_commit = true;
+ }
+
/* Each of the 8 channel enables is considered for whether each
* dword is written.
*/
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
- brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
+ brw_set_src0(p, send, header);
+ if (intel->gen < 6)
+ send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_write_message(p, send,
255, /* binding table index: stateless access */
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
msg_type,
3, /* mlen */
true, /* header present */
- false, /* pixel scoreboard */
- 0, /* rlen */
+ false, /* not a render target write */
+ write_commit, /* rlen */
false, /* eot */
- false /* commit */);
+ write_commit);
}
void
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
+ if (intel->gen < 6)
+ send->header.destreg__conditionalmod = inst->base_mrf;
brw_set_dp_read_message(p, send,
SURF_INDEX_VERT_CONST_BUFFER,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
- if (intel->gen >= 6) {
+ if (intel->gen == 6) {
generate_math1_gen6(inst, dst, src[0]);
} else {
+ /* Also works for Gen7. */
generate_math1_gen4(inst, dst, src[0]);
}
break;
case SHADER_OPCODE_POW:
- if (intel->gen >= 6) {
+ case SHADER_OPCODE_INT_QUOTIENT:
+ case SHADER_OPCODE_INT_REMAINDER:
+ if (intel->gen >= 7) {
+ generate_math2_gen7(inst, dst, src[0], src[1]);
+ } else if (intel->gen == 6) {
generate_math2_gen6(inst, dst, src[0], src[1]);
} else {
generate_math2_gen4(inst, dst, src[0], src[1]);
}
break;
+ case SHADER_OPCODE_TEX:
+ case SHADER_OPCODE_TXD:
+ case SHADER_OPCODE_TXF:
+ case SHADER_OPCODE_TXL:
+ case SHADER_OPCODE_TXS:
+ generate_tex(inst, dst, src[0]);
+ break;
+
case VS_OPCODE_URB_WRITE:
generate_urb_write(inst);
break;
bool
vec4_visitor::run()
{
+ if (c->key.userclip_active && !c->key.uses_clip_distance)
+ setup_uniform_clipplane_values();
+
/* Generate VS IR for main(). (the visitor only descends into
* functions called "main").
*/
*/
move_grf_array_access_to_scratch();
move_uniform_array_access_to_pull_constants();
+ pack_uniform_registers();
+ move_push_constants_to_pull_constants();
bool progress;
do {
progress = false;
progress = dead_code_eliminate() || progress;
+ progress = opt_copy_propagation() || progress;
+ progress = opt_algebraic() || progress;
+ progress = opt_compute_to_mrf() || progress;
} while (progress);
- pack_uniform_registers();
if (failed)
return false;
const char *last_annotation_string = NULL;
ir_instruction *last_annotation_ir = NULL;
- int loop_stack_array_size = 16;
- int loop_stack_depth = 0;
- brw_instruction **loop_stack =
- rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
- int *if_depth_in_loop =
- rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
-
-
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
printf("Native code for vertex shader %d:\n", prog->Name);
}
struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
brw_inst->header.predicate_control = inst->predicate;
}
- if_depth_in_loop[loop_stack_depth]++;
break;
case BRW_OPCODE_ELSE:
break;
case BRW_OPCODE_ENDIF:
brw_ENDIF(p);
- if_depth_in_loop[loop_stack_depth]--;
break;
case BRW_OPCODE_DO:
- loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
- if (loop_stack_array_size <= loop_stack_depth) {
- loop_stack_array_size *= 2;
- loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
- loop_stack_array_size);
- if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
- loop_stack_array_size);
- }
- if_depth_in_loop[loop_stack_depth] = 0;
+ brw_DO(p, BRW_EXECUTE_8);
break;
case BRW_OPCODE_BREAK:
- brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
+ brw_BREAK(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
case BRW_OPCODE_CONTINUE:
/* FINISHME: We need to write the loop instruction support still. */
if (intel->gen >= 6)
- gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
+ gen6_CONT(p);
else
- brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
+ brw_CONT(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
- case BRW_OPCODE_WHILE: {
- struct brw_instruction *inst0, *inst1;
- GLuint br = 1;
-
- if (intel->gen >= 5)
- br = 2;
-
- assert(loop_stack_depth > 0);
- loop_stack_depth--;
- inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
- if (intel->gen < 6) {
- /* patch all the BREAK/CONT instructions from last BGNLOOP */
- while (inst0 > loop_stack[loop_stack_depth]) {
- inst0--;
- if (inst0->header.opcode == BRW_OPCODE_BREAK &&
- inst0->bits3.if_else.jump_count == 0) {
- inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
- }
- else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
- inst0->bits3.if_else.jump_count == 0) {
- inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
- }
- }
- }
- }
+ case BRW_OPCODE_WHILE:
+ brw_WHILE(p);
break;
default:
printf("\n");
}
- ralloc_free(loop_stack);
- ralloc_free(if_depth_in_loop);
-
brw_set_uip_jip(p);
/* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
vec4_visitor v(c, prog, shader);
if (!v.run()) {
- prog->LinkStatus = GL_FALSE;
+ prog->LinkStatus = false;
ralloc_strcat(&prog->InfoLog, v.fail_msg);
return false;
}
projects / mesa.git / blobdiff