i965/gs: Avoid DW * DW mul

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index e52256738121d41531f351e0281c68589592ac1a..74fd8c29f28862fd76598ec4956e88ce88401b8c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -92,6 +92,9 @@ vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
       case BRW_REGISTER_TYPE_UD:
         brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
         break;
+      case BRW_REGISTER_TYPE_VF:
+         brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
+         break;
       default:
         unreachable("not reached");
       }
@@ -319,7 +322,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
     * use an implied move from g0 to the first message register.
     */
    if (inst->header_present) {
-      if (brw->gen < 6 && !inst->texture_offset) {
+      if (brw->gen < 6 && !inst->offset) {
          /* Set up an implied move from g0 to the MRF. */
          src = brw_vec8_grf(0, 0);
       } else {
@@ -333,10 +336,10 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 
          brw_set_default_access_mode(p, BRW_ALIGN_1);
 
-         if (inst->texture_offset) {
+         if (inst->offset) {
             /* Set the texel offset bits in DWord 2. */
             brw_MOV(p, get_element_ud(header, 2),
-                    brw_imm_ud(inst->texture_offset));
+                    brw_imm_ud(inst->offset));
          }
 
          brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
@@ -526,13 +529,17 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
     *
     * We can do this with the following EU instruction:
     *
-    *     mul(2) dst.3<1>UD src0<8;2,4>UD src1   { Align1 WE_all }
+    *     mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW   { Align1 WE_all }
     */
    brw_push_insn_state(p);
    brw_set_default_access_mode(p, BRW_ALIGN_1);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+   assert(brw->gen >= 7 &&
+          src1.file == BRW_IMMEDIATE_VALUE &&
+          src1.type == BRW_REGISTER_TYPE_UD &&
+          src1.dw1.ud <= USHRT_MAX);
    brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
-           src1);
+           retype(src1, BRW_REGISTER_TYPE_UW));
    brw_set_default_access_mode(p, BRW_ALIGN_16);
    brw_pop_insn_state(p);
 }
@@ -1180,6 +1187,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
       }
 
       switch (inst->opcode) {
+      case VEC4_OPCODE_UNPACK_UNIFORM:
       case BRW_OPCODE_MOV:
          brw_MOV(p, dst, src[0]);
          break;
@@ -1361,6 +1369,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
       case SHADER_OPCODE_LOG2:
       case SHADER_OPCODE_SIN:
       case SHADER_OPCODE_COS:
+         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
          if (brw->gen >= 7) {
             gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
                       brw_null_reg());
@@ -1374,6 +1383,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
       case SHADER_OPCODE_POW:
       case SHADER_OPCODE_INT_QUOTIENT:
       case SHADER_OPCODE_INT_REMAINDER:
+         assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
          if (brw->gen >= 7) {
             gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
          } else if (brw->gen == 6) {
@@ -1490,6 +1500,48 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_unpack_flags(inst, dst);
          break;
 
+      case VEC4_OPCODE_PACK_BYTES: {
+         /* Is effectively:
+          *
+          *   mov(8) dst<16,4,1>:UB src<4,1,0>:UB
+          *
+          * but destinations' only regioning is horizontal stride, so instead we
+          * have to use two instructions:
+          *
+          *   mov(4) dst<1>:UB     src<4,1,0>:UB
+          *   mov(4) dst.16<1>:UB  src.16<4,1,0>:UB
+          *
+          * where they pack the four bytes from the low and high four DW.
+          */
+         assert(is_power_of_two(dst.dw1.bits.writemask) &&
+                dst.dw1.bits.writemask != 0);
+         unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
+
+         dst.type = BRW_REGISTER_TYPE_UB;
+
+         brw_set_default_access_mode(p, BRW_ALIGN_1);
+
+         src[0].type = BRW_REGISTER_TYPE_UB;
+         src[0].vstride = BRW_VERTICAL_STRIDE_4;
+         src[0].width = BRW_WIDTH_1;
+         src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
+         dst.subnr = offset * 4;
+         struct brw_inst *insn = brw_MOV(p, dst, src[0]);
+         brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
+         brw_inst_set_no_dd_clear(brw, insn, true);
+         brw_inst_set_no_dd_check(brw, insn, inst->no_dd_check);
+
+         src[0].subnr = 16;
+         dst.subnr = 16 + offset * 4;
+         insn = brw_MOV(p, dst, src[0]);
+         brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
+         brw_inst_set_no_dd_clear(brw, insn, inst->no_dd_clear);
+         brw_inst_set_no_dd_check(brw, insn, true);
+
+         brw_set_default_access_mode(p, BRW_ALIGN_16);
+         break;
+      }
+
       default:
          if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
             _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
@@ -1500,14 +1552,19 @@ vec4_generator::generate_code(const cfg_t *cfg)
          abort();
       }
 
-      if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
+      if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
+         /* Handled dependency hints in the generator. */
+
+         assert(!inst->conditional_mod);
+      } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
          assert(p->nr_insn == pre_emit_nr_insn + 1 ||
                 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
                  "emitting more than 1 instruction");
 
          brw_inst *last = &p->store[pre_emit_nr_insn];
 
-         brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
+         if (inst->conditional_mod)
+            brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
          brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
          brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
       }