*/
#include "brw_vec4_gs_visitor.h"
+#include "gen6_gs_visitor.h"
const unsigned MAX_GS_INPUT_VERTICES = 6;
vec4_gs_visitor::vec4_gs_visitor(struct brw_context *brw,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
- struct brw_shader *shader,
void *mem_ctx,
bool no_spills)
: vec4_visitor(brw, &c->base, &c->gp->program.Base, &c->key.base,
- &c->prog_data.base, prog, shader, mem_ctx,
- INTEL_DEBUG & DEBUG_GS, no_spills),
+ &c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx,
+ no_spills,
+ ST_GS, ST_GS_WRITTEN, ST_GS_RESET),
c(c)
{
}
dst_reg *
vec4_gs_visitor::make_reg_for_system_value(ir_variable *ir)
{
- /* Geometry shaders don't use any system values. */
- assert(!"Unreached");
- return NULL;
+ dst_reg *reg = new(mem_ctx) dst_reg(this, ir->type);
+
+ switch (ir->data.location) {
+ case SYSTEM_VALUE_INVOCATION_ID:
+ this->current_annotation = "initialize gl_InvocationID";
+ emit(GS_OPCODE_GET_INSTANCE_ID, *reg);
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ return reg;
}
{
int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES];
- /* If we are in dual instanced mode, then attributes are going to be
- * interleaved, so one register contains two attribute slots.
+ /* If we are in dual instanced or single mode, then attributes are going
+ * to be interleaved, so one register contains two attribute slots.
*/
- int attributes_per_reg = c->prog_data.dual_instanced_dispatch ? 2 : 1;
+ int attributes_per_reg =
+ c->prog_data.dispatch_mode == GEN7_GS_DISPATCH_MODE_DUAL_OBJECT ? 1 : 2;
/* If a geometry shader tries to read from an input that wasn't written by
* the vertex shader, that produces undefined results, but it shouldn't
reg = setup_varying_inputs(reg, attribute_map, attributes_per_reg);
- lower_attributes_to_hw_regs(attribute_map,
- c->prog_data.dual_instanced_dispatch);
+ lower_attributes_to_hw_regs(attribute_map, attributes_per_reg > 1);
this->first_non_payload_grf = reg;
}
*/
this->current_annotation = "clear r0.2";
dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
- vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+ vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u);
inst->force_writemask_all = true;
/* Create a virtual register to hold the vertex count */
src_reg src(dst);
dst.writemask = WRITEMASK_X;
src.swizzle = BRW_SWIZZLE_WWWW;
- emit(MOV(dst, src));
+ inst = emit(MOV(dst, src));
+
+ /* In dual instanced dispatch mode, dst has a width of 4, so we need
+ * to make sure the MOV happens regardless of which channels are
+ * enabled.
+ */
+ inst->force_writemask_all = true;
}
}
vec4_gs_visitor::emit_program_code()
{
/* We don't support NV_geometry_program4. */
- assert(!"Unreached");
+ unreachable("Unreached");
}
vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE);
inst->offset = c->prog_data.control_data_header_size_hwords;
+
+ /* We need to increment Global Offset by 1 to make room for Broadwell's
+ * extra "Vertex Count" payload at the beginning of the URB entry.
+ */
+ if (brw->gen >= 8)
+ inst->offset++;
+
inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
return inst;
}
* setup_attributes() will remap our accesses to the actual input array.
*/
ir_dereference_variable *deref_var = ir->array->as_dereference_variable();
- if (deref_var && deref_var->var->mode == ir_var_shader_in)
+ if (deref_var && deref_var->var->data.mode == ir_var_shader_in)
return BRW_VARYING_SLOT_COUNT;
else
return vec4_visitor::compute_array_stride(ir);
src_reg channel_mask(this, glsl_type::uint_type);
inst = emit(SHL(dst_reg(channel_mask), one, channel));
inst->force_writemask_all = true;
- emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask));
+ emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask),
+ channel_mask);
emit(GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask);
}
inst->force_writemask_all = true;
inst = emit(GS_OPCODE_URB_WRITE);
inst->urb_write_flags = urb_write_flags;
+ /* We need to increment Global Offset by 256-bits to make room for
+ * Broadwell's extra "Vertex Count" payload at the beginning of the
+ * URB entry. Since this is an OWord message, Global Offset is counted
+ * in 128-bit units, so we must set it to 2.
+ */
+ if (brw->gen >= 8)
+ inst->offset = 2;
inst->base_mrf = base_mrf;
inst->mlen = 2;
}
emit(BRW_OPCODE_ENDIF);
}
+void
+vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id)
+{
+ /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
+
+ /* Note: we are calling this *before* increasing vertex_count, so
+ * this->vertex_count == vertex_count - 1 in the formula above.
+ */
+
+ /* Stream mode uses 2 bits per vertex */
+ assert(c->control_data_bits_per_vertex == 2);
+
+ /* Must be a valid stream */
+ assert(stream_id >= 0 && stream_id < MAX_VERTEX_STREAMS);
+
+ /* Control data bits are initialized to 0 so we don't have to set any
+ * bits when sending vertices to stream 0.
+ */
+ if (stream_id == 0)
+ return;
+
+ /* reg::sid = stream_id */
+ src_reg sid(this, glsl_type::uint_type);
+ emit(MOV(dst_reg(sid), stream_id));
+
+ /* reg:shift_count = 2 * (vertex_count - 1) */
+ src_reg shift_count(this, glsl_type::uint_type);
+ emit(SHL(dst_reg(shift_count), this->vertex_count, 1u));
+
+ /* Note: we're relying on the fact that the GEN SHL instruction only pays
+ * attention to the lower 5 bits of its second source argument, so on this
+ * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
+ * stream_id << ((2 * (vertex_count - 1)) % 32).
+ */
+ src_reg mask(this, glsl_type::uint_type);
+ emit(SHL(dst_reg(mask), sid, shift_count));
+ emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask));
+}
void
-vec4_gs_visitor::visit(ir_emit_vertex *)
+vec4_gs_visitor::visit(ir_emit_vertex *ir)
{
this->current_annotation = "emit vertex: safety check";
this->current_annotation = "emit vertex: vertex data";
emit_vertex();
+ /* In stream mode we have to set control data bits for all vertices
+ * unless we have disabled control data bits completely (which we do
+ * do for GL_POINTS outputs that don't use streams).
+ */
+ if (c->control_data_header_size_bits > 0 &&
+ c->prog_data.control_data_format ==
+ GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
+ this->current_annotation = "emit vertex: Stream control data bits";
+ set_stream_control_data_bits(ir->stream_id());
+ }
+
this->current_annotation = "emit vertex: increment vertex count";
emit(ADD(dst_reg(this->vertex_count), this->vertex_count,
src_reg(1u)));
emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask));
}
+static const unsigned *
+generate_assembly(struct brw_context *brw,
+ struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
+ struct brw_vue_prog_data *prog_data,
+ void *mem_ctx,
+ const cfg_t *cfg,
+ unsigned *final_assembly_size)
+{
+ vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
+ INTEL_DEBUG & DEBUG_GS, "geometry", "GS");
+ return g.generate_assembly(cfg, final_assembly_size);
+}
extern "C" const unsigned *
brw_gs_emit(struct brw_context *brw,
void *mem_ctx,
unsigned *final_assembly_size)
{
- struct brw_shader *shader =
- (brw_shader *) prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
-
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
- printf("GLSL IR for native geometry shader %d:\n", prog->Name);
- _mesa_print_ir(shader->ir, NULL);
- printf("\n\n");
+ struct brw_shader *shader =
+ (brw_shader *) prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
+
+ brw_dump_ir("geometry", prog, &shader->base, NULL);
+ }
+
+ if (brw->gen >= 7) {
+ /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
+ * so without spilling. If the GS invocations count > 1, then we can't use
+ * dual object mode.
+ */
+ if (c->prog_data.invocations <= 1 &&
+ likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
+ c->prog_data.dispatch_mode = GEN7_GS_DISPATCH_MODE_DUAL_OBJECT;
+
+ vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */);
+ if (v.run()) {
+ return generate_assembly(brw, prog, &c->gp->program.Base,
+ &c->prog_data.base, mem_ctx, v.cfg,
+ final_assembly_size);
+ }
+ }
}
- /* Assume the geometry shader will use DUAL_OBJECT dispatch for now. */
- c->prog_data.dual_instanced_dispatch = false;
+ /* Either we failed to compile in DUAL_OBJECT mode (probably because it
+ * would have required spilling) or DUAL_OBJECT mode is disabled. So fall
+ * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers.
+ *
+ * FIXME: Single dispatch mode requires that the driver can handle
+ * interleaving of input registers, but this is already supported (dual
+ * instance mode has the same requirement). However, to take full advantage
+ * of single dispatch mode to reduce register pressure we would also need to
+ * do interleaved outputs, but currently, the vec4 visitor and generator
+ * classes do not support this, so at the moment register pressure in
+ * single and dual instance modes is the same.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS"
+ * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely
+ * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode
+ * is also supported. When InstanceCount=1 (one instance per object) software
+ * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be
+ * the best choice for performance, followed by SINGLE mode."
+ *
+ * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE
+ * mode is more performant when invocations > 1. Gen6 only supports
+ * SINGLE mode.
+ */
+ if (c->prog_data.invocations <= 1 || brw->gen < 7)
+ c->prog_data.dispatch_mode = GEN7_GS_DISPATCH_MODE_SINGLE;
+ else
+ c->prog_data.dispatch_mode = GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE;
+
+ vec4_gs_visitor *gs = NULL;
+ const unsigned *ret = NULL;
- vec4_gs_visitor v(brw, c, prog, shader, mem_ctx, false /* no_spills */);
- if (!v.run()) {
+ if (brw->gen >= 7)
+ gs = new vec4_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */);
+ else
+ gs = new gen6_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */);
+
+ if (!gs->run()) {
prog->LinkStatus = false;
- ralloc_strcat(&prog->InfoLog, v.fail_msg);
- return NULL;
+ ralloc_strcat(&prog->InfoLog, gs->fail_msg);
+ } else {
+ ret = generate_assembly(brw, prog, &c->gp->program.Base,
+ &c->prog_data.base, mem_ctx, gs->cfg,
+ final_assembly_size);
}
- vec4_generator g(brw, prog, &c->gp->program.Base, &c->prog_data.base,
- mem_ctx, INTEL_DEBUG & DEBUG_GS);
- const unsigned *generated =
- g.generate_assembly(&v.instructions, final_assembly_size);
-
- return generated;
+ delete gs;
+ return ret;
}
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