*/
#include "brw_vec4_gs_visitor.h"
-
-const unsigned MAX_GS_INPUT_VERTICES = 6;
+#include "gen6_gs_visitor.h"
+#include "brw_fs.h"
+#include "brw_nir.h"
namespace brw {
-vec4_gs_visitor::vec4_gs_visitor(struct brw_context *brw,
+vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler,
+ void *log_data,
struct brw_gs_compile *c,
- struct gl_shader_program *prog,
+ struct brw_gs_prog_data *prog_data,
+ const nir_shader *shader,
void *mem_ctx,
- bool no_spills)
- : vec4_visitor(brw, &c->base, &c->gp->program.Base, &c->key.base,
- &c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx,
- INTEL_DEBUG & DEBUG_GS, no_spills,
- ST_GS, ST_GS_WRITTEN, ST_GS_RESET),
- c(c)
+ bool no_spills,
+ int shader_time_index)
+ : vec4_visitor(compiler, log_data, &c->key.tex,
+ &prog_data->base, shader, mem_ctx,
+ no_spills, shader_time_index),
+ c(c),
+ gs_prog_data(prog_data)
{
}
dst_reg *
-vec4_gs_visitor::make_reg_for_system_value(ir_variable *ir)
+vec4_gs_visitor::make_reg_for_system_value(int location)
{
- dst_reg *reg = new(mem_ctx) dst_reg(this, ir->type);
+ dst_reg *reg = new(mem_ctx) dst_reg(this, glsl_type::int_type);
- switch (ir->data.location) {
+ switch (location) {
case SYSTEM_VALUE_INVOCATION_ID:
this->current_annotation = "initialize gl_InvocationID";
emit(GS_OPCODE_GET_INSTANCE_ID, *reg);
* so the total number of input slots that will be delivered to the GS (and
* thus the stride of the input arrays) is urb_read_length * 2.
*/
- const unsigned num_input_vertices = c->gp->program.VerticesIn;
+ const unsigned num_input_vertices = nir->info.gs.vertices_in;
assert(num_input_vertices <= MAX_GS_INPUT_VERTICES);
- unsigned input_array_stride = c->prog_data.base.urb_read_length * 2;
+ unsigned input_array_stride = prog_data->urb_read_length * 2;
for (int slot = 0; slot < c->input_vue_map.num_slots; slot++) {
int varying = c->input_vue_map.slot_to_varying[slot];
{
int attribute_map[BRW_VARYING_SLOT_COUNT * MAX_GS_INPUT_VERTICES];
- /* If we are in dual instanced mode, then attributes are going to be
- * interleaved, so one register contains two attribute slots.
+ /* If we are in dual instanced or single mode, then attributes are going
+ * to be interleaved, so one register contains two attribute slots.
*/
- int attributes_per_reg = c->prog_data.dual_instanced_dispatch ? 2 : 1;
+ int attributes_per_reg =
+ prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
/* If a geometry shader tries to read from an input that wasn't written by
* the vertex shader, that produces undefined results, but it shouldn't
reg++;
/* If the shader uses gl_PrimitiveIDIn, that goes in r1. */
- if (c->prog_data.include_primitive_id)
+ if (gs_prog_data->include_primitive_id)
attribute_map[VARYING_SLOT_PRIMITIVE_ID] = attributes_per_reg * reg++;
reg = setup_uniforms(reg);
reg = setup_varying_inputs(reg, attribute_map, attributes_per_reg);
- lower_attributes_to_hw_regs(attribute_map,
- c->prog_data.dual_instanced_dispatch);
+ lower_attributes_to_hw_regs(attribute_map, attributes_per_reg > 1);
this->first_non_payload_grf = reg;
}
*/
this->current_annotation = "clear r0.2";
dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
- vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+ vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u));
inst->force_writemask_all = true;
/* Create a virtual register to hold the vertex count */
/* Initialize the vertex_count register to 0 */
this->current_annotation = "initialize vertex_count";
- inst = emit(MOV(dst_reg(this->vertex_count), 0u));
+ inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u)));
inst->force_writemask_all = true;
if (c->control_data_header_size_bits > 0) {
*/
if (c->control_data_header_size_bits <= 32) {
this->current_annotation = "initialize control data bits";
- inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
- inst->force_writemask_all = true;
- }
- }
-
- /* If the geometry shader uses the gl_PointSize input, we need to fix it up
- * to account for the fact that the vertex shader stored it in the w
- * component of VARYING_SLOT_PSIZ.
- */
- if (c->gp->program.Base.InputsRead & VARYING_BIT_PSIZ) {
- this->current_annotation = "swizzle gl_PointSize input";
- for (int vertex = 0; vertex < c->gp->program.VerticesIn; vertex++) {
- dst_reg dst(ATTR,
- BRW_VARYING_SLOT_COUNT * vertex + VARYING_SLOT_PSIZ);
- dst.type = BRW_REGISTER_TYPE_F;
- src_reg src(dst);
- dst.writemask = WRITEMASK_X;
- src.swizzle = BRW_SWIZZLE_WWWW;
- inst = emit(MOV(dst, src));
-
- /* In dual instanced dispatch mode, dst has a width of 4, so we need
- * to make sure the MOV happens regardless of which channels are
- * enabled.
- */
+ inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
inst->force_writemask_all = true;
}
}
this->current_annotation = NULL;
}
-
-void
-vec4_gs_visitor::emit_program_code()
-{
- /* We don't support NV_geometry_program4. */
- unreachable("Unreached");
-}
-
-
void
vec4_gs_visitor::emit_thread_end()
{
*/
int base_mrf = 1;
+ bool static_vertex_count = gs_prog_data->static_vertex_count != -1;
+
+ /* If the previous instruction was a URB write, we don't need to issue
+ * a second one - we can just set the EOT bit on the previous write.
+ *
+ * Skip this on Gen8+ unless there's a static vertex count, as we also
+ * need to write the vertex count out, and combining the two may not be
+ * possible (or at least not straightforward).
+ */
+ vec4_instruction *last = (vec4_instruction *) instructions.get_tail();
+ if (last && last->opcode == GS_OPCODE_URB_WRITE &&
+ !(INTEL_DEBUG & DEBUG_SHADER_TIME) &&
+ devinfo->gen >= 8 && static_vertex_count) {
+ last->urb_write_flags = BRW_URB_WRITE_EOT | last->urb_write_flags;
+ return;
+ }
+
current_annotation = "thread end";
dst_reg mrf_reg(MRF, base_mrf);
src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
vec4_instruction *inst = emit(MOV(mrf_reg, r0));
inst->force_writemask_all = true;
- emit(GS_OPCODE_SET_VERTEX_COUNT, mrf_reg, this->vertex_count);
+ if (devinfo->gen < 8 || !static_vertex_count)
+ emit(GS_OPCODE_SET_VERTEX_COUNT, mrf_reg, this->vertex_count);
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
emit_shader_time_end();
inst = emit(GS_OPCODE_THREAD_END);
inst->base_mrf = base_mrf;
- inst->mlen = 1;
+ inst->mlen = devinfo->gen >= 8 && !static_vertex_count ? 2 : 1;
}
vec4_instruction *inst = emit(MOV(mrf_reg, r0));
inst->force_writemask_all = true;
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count,
- (uint32_t) c->prog_data.output_vertex_size_hwords);
+ brw_imm_ud(gs_prog_data->output_vertex_size_hwords));
}
(void) complete;
vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE);
- inst->offset = c->prog_data.control_data_header_size_hwords;
+ inst->offset = gs_prog_data->control_data_header_size_hwords;
/* We need to increment Global Offset by 1 to make room for Broadwell's
* extra "Vertex Count" payload at the beginning of the URB entry.
*/
- if (brw->gen >= 8)
+ if (devinfo->gen >= 8 && gs_prog_data->static_vertex_count == -1)
inst->offset++;
inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
}
-int
-vec4_gs_visitor::compute_array_stride(ir_dereference_array *ir)
-{
- /* Geometry shader inputs are arrays, but they use an unusual array layout:
- * instead of all array elements for a given geometry shader input being
- * stored consecutively, all geometry shader inputs are interleaved into
- * one giant array. At this stage of compilation, we assume that the
- * stride of the array is BRW_VARYING_SLOT_COUNT. Later,
- * setup_attributes() will remap our accesses to the actual input array.
- */
- ir_dereference_variable *deref_var = ir->array->as_dereference_variable();
- if (deref_var && deref_var->var->data.mode == ir_var_shader_in)
- return BRW_VARYING_SLOT_COUNT;
- else
- return vec4_visitor::compute_array_stride(ir);
-}
-
-
/**
* Write out a batch of 32 control data bits from the control_data_bits
* register to the URB.
if (c->control_data_header_size_bits > 128)
urb_write_flags = urb_write_flags | BRW_URB_WRITE_PER_SLOT_OFFSET;
- /* If vertex_count is 0, then no control data bits have been accumulated
- * yet, so we should do nothing.
+ /* If we are using either channel masks or a per-slot offset, then we
+ * need to figure out which DWORD we are trying to write to, using the
+ * formula:
+ *
+ * dword_index = (vertex_count - 1) * bits_per_vertex / 32
+ *
+ * Since bits_per_vertex is a power of two, and is known at compile
+ * time, this can be optimized to:
+ *
+ * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
+ */
+ src_reg dword_index(this, glsl_type::uint_type);
+ if (urb_write_flags) {
+ src_reg prev_count(this, glsl_type::uint_type);
+ emit(ADD(dst_reg(prev_count), this->vertex_count,
+ brw_imm_ud(0xffffffffu)));
+ unsigned log2_bits_per_vertex =
+ _mesa_fls(c->control_data_bits_per_vertex);
+ emit(SHR(dst_reg(dword_index), prev_count,
+ brw_imm_ud(6 - log2_bits_per_vertex)));
+ }
+
+ /* Start building the URB write message. The first MRF gets a copy of
+ * R0.
*/
- emit(CMP(dst_null_d(), this->vertex_count, 0u, BRW_CONDITIONAL_NEQ));
- emit(IF(BRW_PREDICATE_NORMAL));
- {
- /* If we are using either channel masks or a per-slot offset, then we
- * need to figure out which DWORD we are trying to write to, using the
- * formula:
- *
- * dword_index = (vertex_count - 1) * bits_per_vertex / 32
- *
- * Since bits_per_vertex is a power of two, and is known at compile
- * time, this can be optimized to:
- *
- * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
+ int base_mrf = 1;
+ dst_reg mrf_reg(MRF, base_mrf);
+ src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+ vec4_instruction *inst = emit(MOV(mrf_reg, r0));
+ inst->force_writemask_all = true;
+
+ if (urb_write_flags & BRW_URB_WRITE_PER_SLOT_OFFSET) {
+ /* Set the per-slot offset to dword_index / 4, to that we'll write to
+ * the appropriate OWORD within the control data header.
*/
- src_reg dword_index(this, glsl_type::uint_type);
- if (urb_write_flags) {
- src_reg prev_count(this, glsl_type::uint_type);
- emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
- unsigned log2_bits_per_vertex =
- _mesa_fls(c->control_data_bits_per_vertex);
- emit(SHR(dst_reg(dword_index), prev_count,
- (uint32_t) (6 - log2_bits_per_vertex)));
- }
+ src_reg per_slot_offset(this, glsl_type::uint_type);
+ emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u)));
+ emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
+ brw_imm_ud(1u));
+ }
- /* Start building the URB write message. The first MRF gets a copy of
- * R0.
+ if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) {
+ /* Set the channel masks to 1 << (dword_index % 4), so that we'll
+ * write to the appropriate DWORD within the OWORD. We need to do
+ * this computation with force_writemask_all, otherwise garbage data
+ * from invocation 0 might clobber the mask for invocation 1 when
+ * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
+ * together.
*/
- int base_mrf = 1;
- dst_reg mrf_reg(MRF, base_mrf);
- src_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
- vec4_instruction *inst = emit(MOV(mrf_reg, r0));
+ src_reg channel(this, glsl_type::uint_type);
+ inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u)));
inst->force_writemask_all = true;
-
- if (urb_write_flags & BRW_URB_WRITE_PER_SLOT_OFFSET) {
- /* Set the per-slot offset to dword_index / 4, to that we'll write to
- * the appropriate OWORD within the control data header.
- */
- src_reg per_slot_offset(this, glsl_type::uint_type);
- emit(SHR(dst_reg(per_slot_offset), dword_index, 2u));
- emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, 1u);
- }
-
- if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) {
- /* Set the channel masks to 1 << (dword_index % 4), so that we'll
- * write to the appropriate DWORD within the OWORD. We need to do
- * this computation with force_writemask_all, otherwise garbage data
- * from invocation 0 might clobber the mask for invocation 1 when
- * GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
- * together.
- */
- src_reg channel(this, glsl_type::uint_type);
- inst = emit(AND(dst_reg(channel), dword_index, 3u));
- inst->force_writemask_all = true;
- src_reg one(this, glsl_type::uint_type);
- inst = emit(MOV(dst_reg(one), 1u));
- inst->force_writemask_all = true;
- src_reg channel_mask(this, glsl_type::uint_type);
- inst = emit(SHL(dst_reg(channel_mask), one, channel));
- inst->force_writemask_all = true;
- emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask),
- channel_mask);
- emit(GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask);
- }
-
- /* Store the control data bits in the message payload and send it. */
- dst_reg mrf_reg2(MRF, base_mrf + 1);
- inst = emit(MOV(mrf_reg2, this->control_data_bits));
+ src_reg one(this, glsl_type::uint_type);
+ inst = emit(MOV(dst_reg(one), brw_imm_ud(1u)));
inst->force_writemask_all = true;
- inst = emit(GS_OPCODE_URB_WRITE);
- inst->urb_write_flags = urb_write_flags;
- /* We need to increment Global Offset by 256-bits to make room for
- * Broadwell's extra "Vertex Count" payload at the beginning of the
- * URB entry. Since this is an OWord message, Global Offset is counted
- * in 128-bit units, so we must set it to 2.
- */
- if (brw->gen >= 8)
- inst->offset = 2;
- inst->base_mrf = base_mrf;
- inst->mlen = 2;
+ src_reg channel_mask(this, glsl_type::uint_type);
+ inst = emit(SHL(dst_reg(channel_mask), one, channel));
+ inst->force_writemask_all = true;
+ emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask),
+ channel_mask);
+ emit(GS_OPCODE_SET_CHANNEL_MASKS, mrf_reg, channel_mask);
}
- emit(BRW_OPCODE_ENDIF);
+
+ /* Store the control data bits in the message payload and send it. */
+ dst_reg mrf_reg2(MRF, base_mrf + 1);
+ inst = emit(MOV(mrf_reg2, this->control_data_bits));
+ inst->force_writemask_all = true;
+ inst = emit(GS_OPCODE_URB_WRITE);
+ inst->urb_write_flags = urb_write_flags;
+ /* We need to increment Global Offset by 256-bits to make room for
+ * Broadwell's extra "Vertex Count" payload at the beginning of the
+ * URB entry. Since this is an OWord message, Global Offset is counted
+ * in 128-bit units, so we must set it to 2.
+ */
+ if (devinfo->gen >= 8 && gs_prog_data->static_vertex_count == -1)
+ inst->offset = 2;
+ inst->base_mrf = base_mrf;
+ inst->mlen = 2;
}
void
/* reg::sid = stream_id */
src_reg sid(this, glsl_type::uint_type);
- emit(MOV(dst_reg(sid), stream_id));
+ emit(MOV(dst_reg(sid), brw_imm_ud(stream_id)));
/* reg:shift_count = 2 * (vertex_count - 1) */
src_reg shift_count(this, glsl_type::uint_type);
- emit(SHL(dst_reg(shift_count), this->vertex_count, 1u));
+ emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u)));
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this
}
void
-vec4_gs_visitor::visit(ir_emit_vertex *ir)
+vec4_gs_visitor::gs_emit_vertex(int stream_id)
{
this->current_annotation = "emit vertex: safety check";
- /* To ensure that we don't output more vertices than the shader specified
- * using max_vertices, do the logic inside a conditional of the form "if
- * (vertex_count < MAX)"
+ /* Haswell and later hardware ignores the "Render Stream Select" bits
+ * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
+ * and instead sends all primitives down the pipeline for rasterization.
+ * If the SOL stage is enabled, "Render Stream Select" is honored and
+ * primitives bound to non-zero streams are discarded after stream output.
+ *
+ * Since the only purpose of primives sent to non-zero streams is to
+ * be recorded by transform feedback, we can simply discard all geometry
+ * bound to these streams when transform feedback is disabled.
+ */
+ if (stream_id > 0 && !nir->info.has_transform_feedback_varyings)
+ return;
+
+ /* If we're outputting 32 control data bits or less, then we can wait
+ * until the shader is over to output them all. Otherwise we need to
+ * output them as we go. Now is the time to do it, since we're about to
+ * output the vertex_count'th vertex, so it's guaranteed that the
+ * control data bits associated with the (vertex_count - 1)th vertex are
+ * correct.
*/
- unsigned num_output_vertices = c->gp->program.VerticesOut;
- emit(CMP(dst_null_d(), this->vertex_count,
- src_reg(num_output_vertices), BRW_CONDITIONAL_L));
- emit(IF(BRW_PREDICATE_NORMAL));
- {
- /* If we're outputting 32 control data bits or less, then we can wait
- * until the shader is over to output them all. Otherwise we need to
- * output them as we go. Now is the time to do it, since we're about to
- * output the vertex_count'th vertex, so it's guaranteed that the
- * control data bits associated with the (vertex_count - 1)th vertex are
- * correct.
+ if (c->control_data_header_size_bits > 32) {
+ this->current_annotation = "emit vertex: emit control data bits";
+ /* Only emit control data bits if we've finished accumulating a batch
+ * of 32 bits. This is the case when:
+ *
+ * (vertex_count * bits_per_vertex) % 32 == 0
+ *
+ * (in other words, when the last 5 bits of vertex_count *
+ * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
+ * integer n (which is always the case, since bits_per_vertex is
+ * always 1 or 2), this is equivalent to requiring that the last 5-n
+ * bits of vertex_count are 0:
+ *
+ * vertex_count & (2^(5-n) - 1) == 0
+ *
+ * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
+ * equivalent to:
+ *
+ * vertex_count & (32 / bits_per_vertex - 1) == 0
*/
- if (c->control_data_header_size_bits > 32) {
- this->current_annotation = "emit vertex: emit control data bits";
- /* Only emit control data bits if we've finished accumulating a batch
- * of 32 bits. This is the case when:
- *
- * (vertex_count * bits_per_vertex) % 32 == 0
- *
- * (in other words, when the last 5 bits of vertex_count *
- * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
- * integer n (which is always the case, since bits_per_vertex is
- * always 1 or 2), this is equivalent to requiring that the last 5-n
- * bits of vertex_count are 0:
- *
- * vertex_count & (2^(5-n) - 1) == 0
- *
- * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
- * equivalent to:
- *
- * vertex_count & (32 / bits_per_vertex - 1) == 0
+ vec4_instruction *inst =
+ emit(AND(dst_null_ud(), this->vertex_count,
+ brw_imm_ud(32 / c->control_data_bits_per_vertex - 1)));
+ inst->conditional_mod = BRW_CONDITIONAL_Z;
+
+ emit(IF(BRW_PREDICATE_NORMAL));
+ {
+ /* If vertex_count is 0, then no control data bits have been
+ * accumulated yet, so we skip emitting them.
*/
- vec4_instruction *inst =
- emit(AND(dst_null_d(), this->vertex_count,
- (uint32_t) (32 / c->control_data_bits_per_vertex - 1)));
- inst->conditional_mod = BRW_CONDITIONAL_Z;
+ emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u),
+ BRW_CONDITIONAL_NEQ));
emit(IF(BRW_PREDICATE_NORMAL));
- {
- emit_control_data_bits();
-
- /* Reset control_data_bits to 0 so we can start accumulating a new
- * batch.
- *
- * Note: in the case where vertex_count == 0, this neutralizes the
- * effect of any call to EndPrimitive() that the shader may have
- * made before outputting its first vertex.
- */
- inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
- inst->force_writemask_all = true;
- }
+ emit_control_data_bits();
emit(BRW_OPCODE_ENDIF);
- }
-
- this->current_annotation = "emit vertex: vertex data";
- emit_vertex();
- /* In stream mode we have to set control data bits for all vertices
- * unless we have disabled control data bits completely (which we do
- * do for GL_POINTS outputs that don't use streams).
- */
- if (c->control_data_header_size_bits > 0 &&
- c->prog_data.control_data_format ==
- GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
- this->current_annotation = "emit vertex: Stream control data bits";
- set_stream_control_data_bits(ir->stream_id());
+ /* Reset control_data_bits to 0 so we can start accumulating a new
+ * batch.
+ *
+ * Note: in the case where vertex_count == 0, this neutralizes the
+ * effect of any call to EndPrimitive() that the shader may have
+ * made before outputting its first vertex.
+ */
+ inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
+ inst->force_writemask_all = true;
}
+ emit(BRW_OPCODE_ENDIF);
+ }
+
+ this->current_annotation = "emit vertex: vertex data";
+ emit_vertex();
- this->current_annotation = "emit vertex: increment vertex count";
- emit(ADD(dst_reg(this->vertex_count), this->vertex_count,
- src_reg(1u)));
+ /* In stream mode we have to set control data bits for all vertices
+ * unless we have disabled control data bits completely (which we do
+ * do for GL_POINTS outputs that don't use streams).
+ */
+ if (c->control_data_header_size_bits > 0 &&
+ gs_prog_data->control_data_format ==
+ GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID) {
+ this->current_annotation = "emit vertex: Stream control data bits";
+ set_stream_control_data_bits(stream_id);
}
- emit(BRW_OPCODE_ENDIF);
this->current_annotation = NULL;
}
void
-vec4_gs_visitor::visit(ir_end_primitive *)
+vec4_gs_visitor::gs_end_primitive()
{
/* We can only do EndPrimitive() functionality when the control data
* consists of cut bits. Fortunately, the only time it isn't is when the
* output type is points, in which case EndPrimitive() is a no-op.
*/
- if (c->prog_data.control_data_format !=
+ if (gs_prog_data->control_data_format !=
GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT) {
return;
}
/* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
src_reg one(this, glsl_type::uint_type);
- emit(MOV(dst_reg(one), 1u));
+ emit(MOV(dst_reg(one), brw_imm_ud(1u)));
src_reg prev_count(this, glsl_type::uint_type);
- emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
+ emit(ADD(dst_reg(prev_count), this->vertex_count, brw_imm_ud(0xffffffffu)));
src_reg mask(this, glsl_type::uint_type);
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this
emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask));
}
-static const unsigned *
-generate_assembly(struct brw_context *brw,
- struct gl_shader_program *shader_prog,
- struct gl_program *prog,
- struct brw_vec4_prog_data *prog_data,
- void *mem_ctx,
- exec_list *instructions,
- unsigned *final_assembly_size)
-{
- vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
- INTEL_DEBUG & DEBUG_GS);
- return g.generate_assembly(instructions, final_assembly_size);
-}
-
extern "C" const unsigned *
-brw_gs_emit(struct brw_context *brw,
- struct gl_shader_program *prog,
- struct brw_gs_compile *c,
- void *mem_ctx,
- unsigned *final_assembly_size)
+brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
+ void *mem_ctx,
+ const struct brw_gs_prog_key *key,
+ struct brw_gs_prog_data *prog_data,
+ const nir_shader *src_shader,
+ struct gl_shader_program *shader_prog,
+ int shader_time_index,
+ unsigned *final_assembly_size,
+ char **error_str)
{
- if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
- struct brw_shader *shader =
- (brw_shader *) prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
+ struct brw_gs_compile c;
+ memset(&c, 0, sizeof(c));
+ c.key = *key;
+
+ const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY];
+ nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
+
+ /* The GLSL linker will have already matched up GS inputs and the outputs
+ * of prior stages. The driver does extend VS outputs in some cases, but
+ * only for legacy OpenGL or Gen4-5 hardware, neither of which offer
+ * geometry shader support. So we can safely ignore that.
+ *
+ * For SSO pipelines, we use a fixed VUE map layout based on variable
+ * locations, so we can rely on rendezvous-by-location making this work.
+ *
+ * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not
+ * written by previous stages and shows up via payload magic.
+ */
+ GLbitfield64 inputs_read =
+ shader->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID;
+ brw_compute_vue_map(compiler->devinfo,
+ &c.input_vue_map, inputs_read,
+ shader->info.separate_shader);
+
+ shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
+ is_scalar);
+ brw_nir_lower_vue_inputs(shader, is_scalar, &c.input_vue_map);
+ brw_nir_lower_vue_outputs(shader, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
+
+ prog_data->include_primitive_id =
+ (shader->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;
+
+ prog_data->invocations = shader->info.gs.invocations;
+
+ if (compiler->devinfo->gen >= 8)
+ prog_data->static_vertex_count = nir_gs_count_vertices(shader);
+
+ if (compiler->devinfo->gen >= 7) {
+ if (shader->info.gs.output_primitive == GL_POINTS) {
+ /* When the output type is points, the geometry shader may output data
+ * to multiple streams, and EndPrimitive() has no effect. So we
+ * configure the hardware to interpret the control data as stream ID.
+ */
+ prog_data->control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID;
+
+ /* We only have to emit control bits if we are using streams */
+ if (shader_prog && shader_prog->Geom.UsesStreams)
+ c.control_data_bits_per_vertex = 2;
+ else
+ c.control_data_bits_per_vertex = 0;
+ } else {
+ /* When the output type is triangle_strip or line_strip, EndPrimitive()
+ * may be used to terminate the current strip and start a new one
+ * (similar to primitive restart), and outputting data to multiple
+ * streams is not supported. So we configure the hardware to interpret
+ * the control data as EndPrimitive information (a.k.a. "cut bits").
+ */
+ prog_data->control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT;
- brw_dump_ir(brw, "geometry", prog, &shader->base, NULL);
+ /* We only need to output control data if the shader actually calls
+ * EndPrimitive().
+ */
+ c.control_data_bits_per_vertex =
+ shader->info.gs.uses_end_primitive ? 1 : 0;
+ }
+ } else {
+ /* There are no control data bits in gen6. */
+ c.control_data_bits_per_vertex = 0;
+
+ /* If it is using transform feedback, enable it */
+ if (shader->info.has_transform_feedback_varyings)
+ prog_data->gen6_xfb_enabled = true;
+ else
+ prog_data->gen6_xfb_enabled = false;
}
+ c.control_data_header_size_bits =
+ shader->info.gs.vertices_out * c.control_data_bits_per_vertex;
- /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
- * so without spilling. If the GS invocations count > 1, then we can't use
- * dual object mode.
+ /* 1 HWORD = 32 bytes = 256 bits */
+ prog_data->control_data_header_size_hwords =
+ ALIGN(c.control_data_header_size_bits, 256) / 256;
+
+ /* Compute the output vertex size.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 STATE_GS - Output Vertex
+ * Size (p168):
+ *
+ * [0,62] indicating [1,63] 16B units
+ *
+ * Specifies the size of each vertex stored in the GS output entry
+ * (following any Control Header data) as a number of 128-bit units
+ * (minus one).
+ *
+ * Programming Restrictions: The vertex size must be programmed as a
+ * multiple of 32B units with the following exception: Rendering is
+ * disabled (as per SOL stage state) and the vertex size output by the
+ * GS thread is 16B.
+ *
+ * If rendering is enabled (as per SOL state) the vertex size must be
+ * programmed as a multiple of 32B units. In other words, the only time
+ * software can program a vertex size with an odd number of 16B units
+ * is when rendering is disabled.
+ *
+ * Note: B=bytes in the above text.
+ *
+ * It doesn't seem worth the extra trouble to optimize the case where the
+ * vertex size is 16B (especially since this would require special-casing
+ * the GEN assembly that writes to the URB). So we just set the vertex
+ * size to a multiple of 32B (2 vec4's) in all cases.
+ *
+ * The maximum output vertex size is 62*16 = 992 bytes (31 hwords). We
+ * budget that as follows:
+ *
+ * 512 bytes for varyings (a varying component is 4 bytes and
+ * gl_MaxGeometryOutputComponents = 128)
+ * 16 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
+ * bytes)
+ * 16 bytes overhead for gl_Position (we allocate it a slot in the VUE
+ * even if it's not used)
+ * 32 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
+ * whenever clip planes are enabled, even if the shader doesn't
+ * write to gl_ClipDistance)
+ * 16 bytes overhead since the VUE size must be a multiple of 32 bytes
+ * (see below)--this causes up to 1 VUE slot to be wasted
+ * 400 bytes available for varying packing overhead
+ *
+ * Worst-case varying packing overhead is 3/4 of a varying slot (12 bytes)
+ * per interpolation type, so this is plenty.
+ *
+ */
+ unsigned output_vertex_size_bytes = prog_data->base.vue_map.num_slots * 16;
+ assert(compiler->devinfo->gen == 6 ||
+ output_vertex_size_bytes <= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES);
+ prog_data->output_vertex_size_hwords =
+ ALIGN(output_vertex_size_bytes, 32) / 32;
+
+ /* Compute URB entry size. The maximum allowed URB entry size is 32k.
+ * That divides up as follows:
+ *
+ * 64 bytes for the control data header (cut indices or StreamID bits)
+ * 4096 bytes for varyings (a varying component is 4 bytes and
+ * gl_MaxGeometryTotalOutputComponents = 1024)
+ * 4096 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16
+ * bytes/vertex and gl_MaxGeometryOutputVertices is 256)
+ * 4096 bytes overhead for gl_Position (we allocate it a slot in the VUE
+ * even if it's not used)
+ * 8192 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots
+ * whenever clip planes are enabled, even if the shader doesn't
+ * write to gl_ClipDistance)
+ * 4096 bytes overhead since the VUE size must be a multiple of 32
+ * bytes (see above)--this causes up to 1 VUE slot to be wasted
+ * 8128 bytes available for varying packing overhead
+ *
+ * Worst-case varying packing overhead is 3/4 of a varying slot per
+ * interpolation type, which works out to 3072 bytes, so this would allow
+ * us to accommodate 2 interpolation types without any danger of running
+ * out of URB space.
+ *
+ * In practice, the risk of running out of URB space is very small, since
+ * the above figures are all worst-case, and most of them scale with the
+ * number of output vertices. So we'll just calculate the amount of space
+ * we need, and if it's too large, fail to compile.
+ *
+ * The above is for gen7+ where we have a single URB entry that will hold
+ * all the output. In gen6, we will have to allocate URB entries for every
+ * vertex we emit, so our URB entries only need to be large enough to hold
+ * a single vertex. Also, gen6 does not have a control data header.
+ */
+ unsigned output_size_bytes;
+ if (compiler->devinfo->gen >= 7) {
+ output_size_bytes =
+ prog_data->output_vertex_size_hwords * 32 * shader->info.gs.vertices_out;
+ output_size_bytes += 32 * prog_data->control_data_header_size_hwords;
+ } else {
+ output_size_bytes = prog_data->output_vertex_size_hwords * 32;
+ }
+
+ /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output,
+ * which comes before the control header.
+ */
+ if (compiler->devinfo->gen >= 8)
+ output_size_bytes += 32;
+
+ assert(output_size_bytes >= 1);
+ unsigned max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES;
+ if (compiler->devinfo->gen == 6)
+ max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
+ if (output_size_bytes > max_output_size_bytes)
+ return NULL;
+
+
+ /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and
+ * a multiple of 128 bytes in gen6.
+ */
+ if (compiler->devinfo->gen >= 7)
+ prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
+ else
+ prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128;
+
+ prog_data->output_topology =
+ get_hw_prim_for_gl_prim(shader->info.gs.output_primitive);
+
+ prog_data->vertices_in = shader->info.gs.vertices_in;
+
+ /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
+ * need to program a URB read length of ceiling(num_slots / 2).
*/
- if (c->prog_data.invocations <= 1 &&
- likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
- c->prog_data.dual_instanced_dispatch = false;
-
- vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */);
- if (v.run()) {
- return generate_assembly(brw, prog, &c->gp->program.Base,
- &c->prog_data.base, mem_ctx, &v.instructions,
- final_assembly_size);
+ prog_data->base.urb_read_length = (c.input_vue_map.num_slots + 1) / 2;
+
+ /* Now that prog_data setup is done, we are ready to actually compile the
+ * program.
+ */
+ if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
+ fprintf(stderr, "GS Input ");
+ brw_print_vue_map(stderr, &c.input_vue_map);
+ fprintf(stderr, "GS Output ");
+ brw_print_vue_map(stderr, &prog_data->base.vue_map);
+ }
+
+ if (is_scalar) {
+ fs_visitor v(compiler, log_data, mem_ctx, &c, prog_data, shader,
+ shader_time_index);
+ if (v.run_gs()) {
+ prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
+ prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
+
+ fs_generator g(compiler, log_data, mem_ctx, &c.key,
+ &prog_data->base.base, v.promoted_constants,
+ false, MESA_SHADER_GEOMETRY);
+ if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
+ const char *label =
+ shader->info.label ? shader->info.label : "unnamed";
+ char *name = ralloc_asprintf(mem_ctx, "%s geometry shader %s",
+ label, shader->info.name);
+ g.enable_debug(name);
+ }
+ g.generate_code(v.cfg, 8);
+ return g.get_assembly(final_assembly_size);
+ }
+ }
+
+ if (compiler->devinfo->gen >= 7) {
+ /* Compile the geometry shader in DUAL_OBJECT dispatch mode, if we can do
+ * so without spilling. If the GS invocations count > 1, then we can't use
+ * dual object mode.
+ */
+ if (prog_data->invocations <= 1 &&
+ likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
+ prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
+
+ vec4_gs_visitor v(compiler, log_data, &c, prog_data, shader,
+ mem_ctx, true /* no_spills */, shader_time_index);
+ if (v.run()) {
+ return brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
+ shader, &prog_data->base, v.cfg,
+ final_assembly_size);
+ }
}
}
/* Either we failed to compile in DUAL_OBJECT mode (probably because it
* would have required spilling) or DUAL_OBJECT mode is disabled. So fall
- * back to DUAL_INSTANCED mode, which consumes fewer registers.
+ * back to DUAL_INSTANCED or SINGLE mode, which consumes fewer registers.
+ *
+ * FIXME: Single dispatch mode requires that the driver can handle
+ * interleaving of input registers, but this is already supported (dual
+ * instance mode has the same requirement). However, to take full advantage
+ * of single dispatch mode to reduce register pressure we would also need to
+ * do interleaved outputs, but currently, the vec4 visitor and generator
+ * classes do not support this, so at the moment register pressure in
+ * single and dual instance modes is the same.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 "3DSTATE_GS"
+ * "If InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely
+ * want to use DUAL_INSTANCE mode for higher performance, but SINGLE mode
+ * is also supported. When InstanceCount=1 (one instance per object) software
+ * can decide which dispatch mode to use. DUAL_OBJECT mode would likely be
+ * the best choice for performance, followed by SINGLE mode."
*
- * FIXME: In an ideal world we'd fall back to SINGLE mode, which would
- * allow us to interleave general purpose registers (resulting in even less
- * likelihood of spilling). But at the moment, the vec4 generator and
- * visitor classes don't have the infrastructure to interleave general
- * purpose registers, so DUAL_INSTANCED is the best we can do.
+ * So SINGLE mode is more performant when invocations == 1 and DUAL_INSTANCE
+ * mode is more performant when invocations > 1. Gen6 only supports
+ * SINGLE mode.
*/
- c->prog_data.dual_instanced_dispatch = true;
+ if (prog_data->invocations <= 1 || compiler->devinfo->gen < 7)
+ prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE;
+ else
+ prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE;
- vec4_gs_visitor v(brw, c, prog, mem_ctx, false /* no_spills */);
- if (!v.run()) {
- prog->LinkStatus = false;
- ralloc_strcat(&prog->InfoLog, v.fail_msg);
- return NULL;
+ vec4_gs_visitor *gs = NULL;
+ const unsigned *ret = NULL;
+
+ if (compiler->devinfo->gen >= 7)
+ gs = new vec4_gs_visitor(compiler, log_data, &c, prog_data,
+ shader, mem_ctx, false /* no_spills */,
+ shader_time_index);
+ else
+ gs = new gen6_gs_visitor(compiler, log_data, &c, prog_data, shader_prog,
+ shader, mem_ctx, false /* no_spills */,
+ shader_time_index);
+
+ if (!gs->run()) {
+ if (error_str)
+ *error_str = ralloc_strdup(mem_ctx, gs->fail_msg);
+ } else {
+ ret = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, shader,
+ &prog_data->base, gs->cfg,
+ final_assembly_size);
}
- return generate_assembly(brw, prog, &c->gp->program.Base, &c->prog_data.base,
- mem_ctx, &v.instructions, final_assembly_size);
+ delete gs;
+ return ret;
}
projects / mesa.git / blobdiff