/* Set use[] for this instruction */
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
- for (unsigned j = 0; j < inst->regs_read(i); j++) {
+ if (inst->src[i].file == VGRF) {
+ for (unsigned j = 0; j < regs_read(inst, i); j++) {
for (int c = 0; c < 4; c++) {
const unsigned v =
var_from_reg(alloc, offset(inst->src[i], j), c);
* are the things that screen off preceding definitions of a
* variable, and thus qualify for being in def[].
*/
- if (inst->dst.file == GRF &&
+ if (inst->dst.file == VGRF &&
(!inst->predicate || inst->opcode == BRW_OPCODE_SEL)) {
- for (unsigned i = 0; i < inst->regs_written; i++) {
+ for (unsigned i = 0; i < regs_written(inst); i++) {
for (int c = 0; c < 4; c++) {
if (inst->dst.writemask & (1 << c)) {
const unsigned v =
int ip = 0;
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
- for (unsigned j = 0; j < inst->regs_read(i); j++) {
+ if (inst->src[i].file == VGRF) {
+ for (unsigned j = 0; j < regs_read(inst, i); j++) {
for (int c = 0; c < 4; c++) {
const unsigned v =
var_from_reg(alloc, offset(inst->src[i], j), c);
}
}
- if (inst->dst.file == GRF) {
- for (unsigned i = 0; i < inst->regs_written; i++) {
+ if (inst->dst.file == VGRF) {
+ for (unsigned i = 0; i < regs_written(inst); i++) {
for (int c = 0; c < 4; c++) {
if (inst->dst.writemask & (1 << c)) {
const unsigned v =