i965: Disable hardware blending if advanced blending is in use.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_live_variables.h

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
index e9d9fa18d0a562e7bbbefd701c32f7907ffe0a0a..12d281eb24551d49d5d0e96097c12a97ee12afbd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
@@ -60,7 +60,7 @@ class vec4_live_variables {
 public:
    DECLARE_RALLOC_CXX_OPERATORS(vec4_live_variables)
 
-   vec4_live_variables(vec4_visitor *v, cfg_t *cfg);
+   vec4_live_variables(const simple_allocator &alloc, cfg_t *cfg);
    ~vec4_live_variables();
 
    int num_vars;
@@ -73,9 +73,28 @@ protected:
    void setup_def_use();
    void compute_live_variables();
 
-   vec4_visitor *v;
+   const simple_allocator &alloc;
    cfg_t *cfg;
    void *mem_ctx;
 };
 
+inline unsigned
+var_from_reg(const simple_allocator &alloc, const src_reg &reg,
+             unsigned c = 0)
+{
+   assert(reg.file == VGRF && reg.nr < alloc.count &&
+          reg.reg_offset < alloc.sizes[reg.nr] && c < 4);
+   return (4 * (alloc.offsets[reg.nr] + reg.reg_offset) +
+           BRW_GET_SWZ(reg.swizzle, c));
+}
+
+inline unsigned
+var_from_reg(const simple_allocator &alloc, const dst_reg &reg,
+             unsigned c = 0)
+{
+   assert(reg.file == VGRF && reg.nr < alloc.count &&
+          reg.reg_offset < alloc.sizes[reg.nr] && c < 4);
+   return 4 * (alloc.offsets[reg.nr] + reg.reg_offset) + c;
+}
+
 } /* namespace brw */