i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 01ca6b5dc897d214339cce8dff657072405f52d3..0b27383777f4aa16ff548f7c845ecb2164ca2bdb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -27,7 +27,7 @@ extern "C" {
 } /* extern "C" */
 
 #include "brw_vec4.h"
-#include "glsl/ir_print_visitor.h"
+#include "brw_vs.h"
 
 using namespace brw;
 
@@ -41,7 +41,7 @@ assign(unsigned int *reg_hw_locations, reg *reg)
    }
 }
 
-void
+bool
 vec4_visitor::reg_allocate_trivial()
 {
    unsigned int hw_reg_mapping[this->virtual_grf_count];
@@ -90,7 +90,10 @@ vec4_visitor::reg_allocate_trivial()
    if (prog_data->total_grf > max_grf) {
       fail("Ran out of regs on trivial allocator (%d/%d)\n",
           prog_data->total_grf, max_grf);
+      return false;
    }
+
+   return true;
 }
 
 static void
@@ -109,6 +112,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
    brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
    ralloc_free(brw->vs.regs);
    brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
+   if (brw->gen >= 6)
+      ra_set_allocate_round_robin(brw->vs.regs);
    ralloc_free(brw->vs.classes);
    brw->vs.classes = ralloc_array(brw, int, class_count + 1);
 
@@ -139,7 +144,7 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
    ra_set_finalize(brw->vs.regs, NULL);
 }
 
-void
+bool
 vec4_visitor::reg_allocate()
 {
    unsigned int hw_reg_mapping[virtual_grf_count];
@@ -151,10 +156,8 @@ vec4_visitor::reg_allocate()
    /* Using the trivial allocator can be useful in debugging undefined
     * register access as a result of broken optimization passes.
     */
-   if (0) {
-      reg_allocate_trivial();
-      return;
-   }
+   if (0)
+      return reg_allocate_trivial();
 
    calculate_live_intervals();
 
@@ -213,7 +216,7 @@ vec4_visitor::reg_allocate()
          spill_reg(reg);
       }
       ralloc_free(g);
-      return;
+      return false;
    }
 
    /* Get the chosen virtual registers for each node, and map virtual
@@ -239,6 +242,8 @@ vec4_visitor::reg_allocate()
    }
 
    ralloc_free(g);
+
+   return true;
 }
 
 void
@@ -343,16 +348,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
       }
 
       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
-         dst_reg spill_reg = inst->dst;
-         inst->dst.reg = virtual_grf_alloc(1);
-
-         /* We don't want a swizzle when reading from the source; read the
-          * whole register and use spill_reg's writemask to select which
-          * channels to write.
-          */
-         src_reg temp = src_reg(inst->dst);
-         temp.swizzle = BRW_SWIZZLE_XYZW;
-         emit_scratch_write(inst, temp, spill_reg, spill_offset);
+         emit_scratch_write(inst, spill_offset);
       }
    }