i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index abba0f2f9b5bc0b7c4c3302d481e49f3ed48d133..0b27383777f4aa16ff548f7c845ecb2164ca2bdb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -27,6 +27,7 @@ extern "C" {
 } /* extern "C" */
 
 #include "brw_vec4.h"
+#include "brw_vs.h"
 
 using namespace brw;
 
@@ -101,8 +102,6 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
                              int class_count,
                              int base_reg_count)
 {
-   struct intel_context *intel = &brw->intel;
-
    /* Compute the total number of registers across all classes. */
    int ra_reg_count = 0;
    for (int i = 0; i < class_count; i++) {
@@ -113,7 +112,7 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
    brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
    ralloc_free(brw->vs.regs);
    brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
-   if (intel->gen >= 6)
+   if (brw->gen >= 6)
       ra_set_allocate_round_robin(brw->vs.regs);
    ralloc_free(brw->vs.classes);
    brw->vs.classes = ralloc_array(brw, int, class_count + 1);