i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index f9ebc3cba2b3fe2af28346de8d6d0dca099e672c..0b27383777f4aa16ff548f7c845ecb2164ca2bdb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -27,7 +27,7 @@ extern "C" {
 } /* extern "C" */
 
 #include "brw_vec4.h"
-#include "glsl/ir_print_visitor.h"
+#include "brw_vs.h"
 
 using namespace brw;
 
@@ -76,7 +76,7 @@ vec4_visitor::reg_allocate_trivial()
         next += this->virtual_grf_sizes[i];
       }
    }
-   prog_data->base.total_grf = next;
+   prog_data->total_grf = next;
 
    foreach_iter(exec_list_iterator, iter, this->instructions) {
       vec4_instruction *inst = (vec4_instruction *)iter.get();
@@ -87,9 +87,9 @@ vec4_visitor::reg_allocate_trivial()
       assign(hw_reg_mapping, &inst->src[2]);
    }
 
-   if (prog_data->base.total_grf > max_grf) {
+   if (prog_data->total_grf > max_grf) {
       fail("Ran out of regs on trivial allocator (%d/%d)\n",
-          prog_data->base.total_grf, max_grf);
+          prog_data->total_grf, max_grf);
       return false;
    }
 
@@ -112,6 +112,8 @@ brw_alloc_reg_set_for_classes(struct brw_context *brw,
    brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
    ralloc_free(brw->vs.regs);
    brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
+   if (brw->gen >= 6)
+      ra_set_allocate_round_robin(brw->vs.regs);
    ralloc_free(brw->vs.classes);
    brw->vs.classes = ralloc_array(brw, int, class_count + 1);
 
@@ -221,12 +223,12 @@ vec4_visitor::reg_allocate()
     * regs in the register classes back down to real hardware reg
     * numbers.
     */
-   prog_data->base.total_grf = first_assigned_grf;
+   prog_data->total_grf = first_assigned_grf;
    for (int i = 0; i < virtual_grf_count; i++) {
       int reg = ra_get_node_reg(g, i);
 
       hw_reg_mapping[i] = first_assigned_grf + brw->vs.ra_reg_to_grf[reg];
-      prog_data->base.total_grf = MAX2(prog_data->base.total_grf,
+      prog_data->total_grf = MAX2(prog_data->total_grf,
                                  hw_reg_mapping[i] + virtual_grf_sizes[i]);
    }
 
@@ -321,7 +323,7 @@ void
 vec4_visitor::spill_reg(int spill_reg_nr)
 {
    assert(virtual_grf_sizes[spill_reg_nr] == 1);
-   unsigned int spill_offset = c->base.last_scratch++;
+   unsigned int spill_offset = c->last_scratch++;
 
    /* Generate spill/unspill instructions for the objects being spilled. */
    foreach_list(node, &this->instructions) {