extern "C" {
#include "main/macros.h"
-#include "program/register_allocate.h"
+#include "util/register_allocate.h"
} /* extern "C" */
#include "brw_vec4.h"
-#include "glsl/ir_print_visitor.h"
+#include "brw_vs.h"
+#include "brw_cfg.h"
using namespace brw;
namespace brw {
static void
-assign(unsigned int *reg_hw_locations, reg *reg)
+assign(unsigned int *reg_hw_locations, backend_reg *reg)
{
if (reg->file == GRF) {
reg->reg = reg_hw_locations[reg->reg];
}
}
-void
+bool
vec4_visitor::reg_allocate_trivial()
{
unsigned int hw_reg_mapping[this->virtual_grf_count];
virtual_grf_used[i] = false;
}
- foreach_iter(exec_list_iterator, iter, this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)iter.get();
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
if (inst->dst.file == GRF)
virtual_grf_used[inst->dst.reg] = true;
}
prog_data->total_grf = next;
- foreach_iter(exec_list_iterator, iter, this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)iter.get();
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
if (prog_data->total_grf > max_grf) {
fail("Ran out of regs on trivial allocator (%d/%d)\n",
prog_data->total_grf, max_grf);
+ return false;
}
+
+ return true;
}
-static void
-brw_alloc_reg_set_for_classes(struct brw_context *brw,
- int *class_sizes,
- int class_count,
- int base_reg_count)
+extern "C" void
+brw_vec4_alloc_reg_set(struct intel_screen *screen)
{
+ int base_reg_count =
+ screen->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+
+ /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
+ * SEND-from-GRF sources cannot be split, so we also need classes for each
+ * potential message length.
+ */
+ const int class_count = 2;
+ const int class_sizes[class_count] = {1, 2};
+
/* Compute the total number of registers across all classes. */
int ra_reg_count = 0;
for (int i = 0; i < class_count; i++) {
ra_reg_count += base_reg_count - (class_sizes[i] - 1);
}
- ralloc_free(brw->vs.ra_reg_to_grf);
- brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
- ralloc_free(brw->vs.regs);
- brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
- ralloc_free(brw->vs.classes);
- brw->vs.classes = ralloc_array(brw, int, class_count + 1);
+ ralloc_free(screen->vec4_reg_set.ra_reg_to_grf);
+ screen->vec4_reg_set.ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count);
+ ralloc_free(screen->vec4_reg_set.regs);
+ screen->vec4_reg_set.regs = ra_alloc_reg_set(screen, ra_reg_count);
+ if (screen->devinfo->gen >= 6)
+ ra_set_allocate_round_robin(screen->vec4_reg_set.regs);
+ ralloc_free(screen->vec4_reg_set.classes);
+ screen->vec4_reg_set.classes = ralloc_array(screen, int, class_count);
/* Now, add the registers to their classes, and add the conflicts
* between them and the base GRF registers (and also each other).
int reg = 0;
for (int i = 0; i < class_count; i++) {
int class_reg_count = base_reg_count - (class_sizes[i] - 1);
- brw->vs.classes[i] = ra_alloc_reg_class(brw->vs.regs);
+ screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
for (int j = 0; j < class_reg_count; j++) {
- ra_class_add_reg(brw->vs.regs, brw->vs.classes[i], reg);
+ ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
- brw->vs.ra_reg_to_grf[reg] = j;
+ screen->vec4_reg_set.ra_reg_to_grf[reg] = j;
for (int base_reg = j;
base_reg < j + class_sizes[i];
base_reg++) {
- ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
+ ra_add_transitive_reg_conflict(screen->vec4_reg_set.regs, base_reg, reg);
}
reg++;
}
assert(reg == ra_reg_count);
- ra_set_finalize(brw->vs.regs, NULL);
+ ra_set_finalize(screen->vec4_reg_set.regs, NULL);
}
void
+vec4_visitor::setup_payload_interference(struct ra_graph *g,
+ int first_payload_node,
+ int reg_node_count)
+{
+ int payload_node_count = this->first_non_payload_grf;
+
+ for (int i = 0; i < payload_node_count; i++) {
+ /* Mark each payload reg node as being allocated to its physical register.
+ *
+ * The alternative would be to have per-physical register classes, which
+ * would just be silly.
+ */
+ ra_set_node_reg(g, first_payload_node + i, i);
+
+ /* For now, just mark each payload node as interfering with every other
+ * node to be allocated.
+ */
+ for (int j = 0; j < reg_node_count; j++) {
+ ra_add_node_interference(g, first_payload_node + i, j);
+ }
+ }
+}
+
+bool
vec4_visitor::reg_allocate()
{
+ struct intel_screen *screen = brw->intelScreen;
unsigned int hw_reg_mapping[virtual_grf_count];
- int first_assigned_grf = this->first_non_payload_grf;
- int base_reg_count = max_grf - first_assigned_grf;
- int class_sizes[base_reg_count];
- int class_count = 0;
+ int payload_reg_count = this->first_non_payload_grf;
/* Using the trivial allocator can be useful in debugging undefined
* register access as a result of broken optimization passes.
*/
- if (0) {
- reg_allocate_trivial();
- return;
- }
+ if (0)
+ return reg_allocate_trivial();
calculate_live_intervals();
- /* Set up the register classes.
- *
- * The base registers store a vec4. However, we'll need larger
- * storage for arrays, structures, and matrices, which will be sets
- * of contiguous registers.
- */
- class_sizes[class_count++] = 1;
-
- for (int r = 0; r < virtual_grf_count; r++) {
- int i;
-
- for (i = 0; i < class_count; i++) {
- if (class_sizes[i] == this->virtual_grf_sizes[r])
- break;
- }
- if (i == class_count) {
- if (this->virtual_grf_sizes[r] >= base_reg_count) {
- fail("Object too large to register allocate.\n");
- }
-
- class_sizes[class_count++] = this->virtual_grf_sizes[r];
- }
- }
-
- brw_alloc_reg_set_for_classes(brw, class_sizes, class_count, base_reg_count);
-
- struct ra_graph *g = ra_alloc_interference_graph(brw->vs.regs,
- virtual_grf_count);
+ int node_count = virtual_grf_count;
+ int first_payload_node = node_count;
+ node_count += payload_reg_count;
+ struct ra_graph *g =
+ ra_alloc_interference_graph(screen->vec4_reg_set.regs, node_count);
for (int i = 0; i < virtual_grf_count; i++) {
- for (int c = 0; c < class_count; c++) {
- if (class_sizes[c] == this->virtual_grf_sizes[i]) {
- ra_set_node_class(g, i, brw->vs.classes[c]);
- break;
- }
- }
+ int size = this->virtual_grf_sizes[i];
+ assert(size >= 1 && size <= 2 &&
+ "Register allocation relies on split_virtual_grfs().");
+ ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
for (int j = 0; j < i; j++) {
if (virtual_grf_interferes(i, j)) {
}
}
- if (!ra_allocate_no_spills(g)) {
+ setup_payload_interference(g, first_payload_node, node_count);
+
+ if (!ra_allocate(g)) {
/* Failed to allocate registers. Spill a reg, and the caller will
* loop back into here to try again.
*/
int reg = choose_spill_reg(g);
- if (reg == -1) {
+ if (this->no_spills) {
+ fail("Failure to register allocate. Reduce number of live "
+ "values to avoid this.");
+ } else if (reg == -1) {
fail("no register to spill\n");
} else {
spill_reg(reg);
}
ralloc_free(g);
- return;
+ return false;
}
/* Get the chosen virtual registers for each node, and map virtual
* regs in the register classes back down to real hardware reg
* numbers.
*/
- prog_data->total_grf = first_assigned_grf;
+ prog_data->total_grf = payload_reg_count;
for (int i = 0; i < virtual_grf_count; i++) {
int reg = ra_get_node_reg(g, i);
- hw_reg_mapping[i] = first_assigned_grf + brw->vs.ra_reg_to_grf[reg];
+ hw_reg_mapping[i] = screen->vec4_reg_set.ra_reg_to_grf[reg];
prog_data->total_grf = MAX2(prog_data->total_grf,
hw_reg_mapping[i] + virtual_grf_sizes[i]);
}
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
}
ralloc_free(g);
+
+ return true;
}
void
* spill/unspill we'll have to do, and guess that the insides of
* loops run 10 times.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF) {
spill_costs[inst->src[i].reg] += loop_scale;
loop_scale /= 10;
break;
- case VS_OPCODE_SCRATCH_READ:
- case VS_OPCODE_SCRATCH_WRITE:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
for (int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF)
no_spill[inst->src[i].reg] = true;
assert(virtual_grf_sizes[spill_reg_nr] == 1);
unsigned int spill_offset = c->last_scratch++;
- /* Generate spill/unspill instructions for the objects being spilled. */
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
+ calculate_cfg();
+ /* Generate spill/unspill instructions for the objects being spilled. */
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
src_reg spill_reg = inst->src[i];
temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
assert(temp.writemask != 0);
- emit_scratch_read(inst, temp, spill_reg, spill_offset);
+ emit_scratch_read(block, inst, temp, spill_reg, spill_offset);
}
}
if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
- dst_reg spill_reg = inst->dst;
- inst->dst.reg = virtual_grf_alloc(1);
-
- /* We don't want a swizzle when reading from the source; read the
- * whole register and use spill_reg's writemask to select which
- * channels to write.
- */
- src_reg temp = src_reg(inst->dst);
- temp.swizzle = BRW_SWIZZLE_XYZW;
- emit_scratch_write(inst, temp, spill_reg, spill_offset);
+ emit_scratch_write(block, inst, spill_offset);
}
}
- this->live_intervals_valid = false;
+ invalidate_live_intervals();
}
} /* namespace brw */
projects / mesa.git / blobdiff